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We have characterized the metal-NC high-k-dielectric flash memories on low-temperature UTB-TFTs. Combined with the advantage of low-voltage operations, the reported planar process is expected to be applicable for 3D integration to meet high-density flash memory requirements. Carrier transport was also confirmed to be Frenkle-Poole emission in (Ti,Dy)O and direct tunneling in Al2O3 due to the different...
In this work, the influence of the temperature variation, in the range of 200K up to 380K, on the performance of biaxially strained FinFETs with high-kappa dielectrics (HfO2), TiN metal gate and undoped body is investigated. It is demonstrated that narrow FinFETs present slightly smaller improvement at lower temperatures on the maximum transconductance (and hence mobility) and transconductance-to-drain...
In this work, fabrication of TSNWFET on SOI with down to 25-nm TiN surrounding gate and 8-nm silicon nanowires is reported with high manufacturability and improved device reliability including reduced junction and gate leakage currents by fully eliminating the bottom parasitic channel existing in previous TSNWFET on bulk Si. And high performance is also obtained to be 1124muA/mum and 1468muA/mum at...
In this paper, we investigate the potentialities and properties of HfSiO/MG/cap/TiN gate stack devices, first by identifying the impact of the TiN thickness and its deposition procedure on the device characteristics, and by exploring the use of TaN vs. TiN as the 1st metal layer (MG). Deeper insight into the caps (e.g., Dy) diffusion mechanism is gained by: a) demonstrating stronger diffusion dependence...
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