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Detailed measurements of front and back channel characteristics in advanced SOI MOSFETs (ultrathin film, metal gate, selective epitaxy of source/drain) are used to reveal the transport properties at the corresponding Si/high-K (HfO2/HfSiON) and Si/SiO2 interfaces. Low-temperature operation magnifies the difference between these two interfaces in terms of carrier mobility, threshold voltage and subthreshold...
In this work, the influence of the temperature variation, in the range of 200K up to 380K, on the performance of biaxially strained FinFETs with high-kappa dielectrics (HfO2), TiN metal gate and undoped body is investigated. It is demonstrated that narrow FinFETs present slightly smaller improvement at lower temperatures on the maximum transconductance (and hence mobility) and transconductance-to-drain...
We propose a novel substrate-bias control scheme for FD-SOI SRAM that suppresses inter-die variability and achieves low-voltage operation. Substrate-bias control circuits automatically detect an inter-die threshold-voltage variation, and then maximize read/write margins of memory cells. We confirmed that a 486-kb SRAM operates at 0.42 V, in which an FS/SF corners can be compensated as much as 0.14...
The successful fabrication of hybrid SOI-GeOI wafers is reported. Process alternatives are documented by detailed characterizations. This co-integration achieves high hole mobility in Ge islands and high electron mobility in Si islands.
We report a bias-dependent, nonlinear body resistance model suitable for accurate characterization of PD/SOI technology. This model is implemented in the surface potential based SOI MOSFET compact model PSP-SOI and experimentally verified for 65 nm PD/SOI technology node.
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