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This paper presents new low power CMOS flash analog-to-digital converter (ADC) using multiple-selection method. As an example of 6-bit flash ADC, we use three extra comparators in our design to divide the next stage into four sections and control the switches whether can proceed to the 4-bit modified flash ADC or not. We use multiple-selection method to let only one section of the 4-bit modified flash...
Signal processing circuits are very useful elements in fuzzy logic, artificial neural network, and image application. In image processing, median filter is adopted to remove pulse noise. In the paper, a real-time CMOS analog median circuit is proposed. Based on current-mirror, current comparison, and some digital logics, a new analog median filter with high-speed low chip area is achieved. By using...
According to mini-LVDS specification, the minimum setup and hold time of the receiver are analyzed. The design of a receiver basing on Chartered-Semiconductor 0.35 mum CMOS process is presented, and a simple simulation method is proposed, which can effectively evaluate performance of the receiver. The simulation results show that the setup and hold time of the receiver are all less than 0.8 ns. The...
A continuous-time phase frequency detector (PFD) based on the conventional tri-state PFD is proposed for fast lock charge pump phase-locked loops (CPPLLs) in this paper. The locking time of the PLL can be substantially reduced with the proposed continuous-time scheme. During the period that the best tracing and acquisition properties are required, the bandwidth of the PLL can be increased to decrease...
The design of a compact low-power highspeed class-AB buffer amplifier for driving the large column line loads of large-size TFT-LCD is presented in this paper. The class-AB buffer amplifier can drive large column line loads up to lOOOpF within 1.28 mus. The proposed class-AB buffer amplifier is implemented with a standard 0.35 mum CMOS 2-poly 4-metal process technology and simulated using HSPICE....
This paper describes a novel charge pumping technique for low-power dc-dc converters by switched capacitors. The proposed configurations were based on the charge-transfer-switch (CTS) topology. In this paper, the problems and possible solutions for conventional static CTS charge pumps will be surveyed. In our study, a novel static CMOS voltage shifter which was called the voltage level controller...
This paper proposes a three-phase BLDC motor brake driver IC. The driver contains five major units that are hall-signal-process-unit, logic-control-unit, speed-control-unit, brake-control-unit and power-driver-unit. First, motor speed is used PWM that can be controlled by frequency instead of traditional voltage control method. Moreover, a new brake structure using frequency-to-voltage converter (FVC)...
A novel and robust un-assisted low-trigger and high-holding voltage silicon controlled rectifier (uSCR) is proposed and realized in a 0.35-mum fully-salicided BiCMOS process. Without using any external trigger circuitry, the uSCR has a trigger voltage as low as 7 V to effectively protect deep submicron MOS circuits and a holding voltage higher than the supply voltage to minimize transient influence...
In this paper, we present a VHF and UHF bands oscillator which mainly composed of a Bi- CMOS active load differential amplifier (Diff. amp). We use H-spice and ADS to verify that the active load differential amplifier oscillator output frequency is 817.1 MHz at 3.3 volts power supply under CIC 0.35 um-GeSi process. We also use discrete devices on bread board to prove the circuit is an oscillator circuit...
The size of LCDs is getting larger in particular , it is essential to compromise the driving ability. So , source drivers with high performance, high resolution, and low power dissipation will achieve more additional value. This paper presents a design and implementation of using 10-bit multiple DAC (digital to analog converter) for the driver , and proposes a rail-to-rail output buffer with low offset...
This paper proposed the design and implementation of novel switching-mode output driver according to off-chip transmission speed. The proposed novel output driver posses the advantages of less power consumption under lower transmission rate and better signal integrity when transmission rate up to 640 Mb/s. The circuits were implemented in a 3.3 v 0.35 um CMOS process. Simulation results demonstrate...
A novel dual-output switched capacitor (SC) DC/DC converter with simultaneous step-up and step- down output voltages was proposed. As well as featuring all merits of classical charge pumps, it features lower-cost and higher-efficiency by using charge capacitor sharing and multiple gain pair techniques. A set of analytical equations were derived to describe its performances and optimize its design...
Abstract-A low voltage low power class-AB operational transconductance amplifier (OTA) used in Sigma-Delta modulator is presented in this paper. To reduce the power consumption under low voltage, a current mirror topology with near rail-to-rail output swing is proposed. Its DC gain is enhanced by gain enhancement architecture without extra power consumption. Moreover, to achieve very low errors and...
This paper describes the design of ultra wideband (UWB) pulse generator circuit. The design is based on source couple logic (SCL) for it's low power and high immune to noise. The design is simulated and result of the circuit is dual pulses with width around 200 p second, which used to encode the bipolar data using 2-input multiplexer. Mainly, in this paper, we concern about pulse generator circuit...
The design of a eight-valued multiplexer using the negative differential resistance (NDR) circuit is demonstrated. The NDR circuit is made of one Si-based metal-oxide-semiconductor field-effect-transistor (MOS) and two SiGe-based heterojunction bipolar transistors (HBT). During suitably arranging the MOS parameters, we can obtain the NDR characteristic in its combined current-voltage curve. First...
In this paper, an improved cascoding CMOS bandgap reference(BGR) without opamp is presented. By incorporating a simple feedback transistor and several resistors into conventional cascoding circuit, the power-supply rejection and 2nd -order curvature compensation circuit is formed. With Spectre tool and 0.35 mum CMOS model, the simulation has been carried out and the results show that the PSRR and...
A CMOS-compatible optical biosensing system based on visible absorption spectroscopy is proposed. Within the compact prototype, the CMOS sensor consisting a P+/Nwell finger photodiode and a transimpedance amplifier (TIA) is implemented in a standard 0.35-mum CMOS technology. The ABTS/H2O2/HRP method is adopted as the ground for medical diagnosis. Experimental results demonstrate that the minimum concentration...
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