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Channel materials with high mobility are needed for future nodes to meet the ITRS requirements of MOSFETs. In this work we assess the performance of Si, Ge, and III-V materials like GaAs, InAs and InSb which may perform better than even very highly strained-Si
Ge pMOS mobilities up to 358 cm2/Vs are demonstrated using a Si-compatible process flow without the incorporation of strain. EOT is approximately 12 Aring with a gate leakage less than 0.01 A/cm 2 at Vt+ 0.6 V. Ge transistors are characterized with gate lengths ranging from 10 mum down to 0.125 mum, the shortest ever reported. We also present the best Ge pMOS drain current to date of 790 muA/mum at...
Due to on-going technology paradigm shift from large-integrity LSI to smart LSI with RF/ubiquitous functions, reductions of "parasitic effects" become main concerns to accomplish low-power and high-quality RF operations with the limited interconnect resource. For the power saving, parasitic capacitance of the local interconnects, or the effective dielectric constant (keff), has to be reduced...
Self-aligned printing (SAP) is a recently developed bottom-up printing technique which utilizes the unique ink droplet motion on heterogeneous surfaces to define nanoscale critical features with high yield and uniformity. It was originally developed with conductive polymers. Here we extend this method to fabrication of functional conductive nanostructures with gold nanoparticle ink that allow achieving...
A novel strained-SiGe n-channel field-effect transistor (nFET) featuring silicon-carbon (Si0.99C0.01) source/drain (S/D) stressors and tensile stress nitride (SiN) liner is demonstrated for the first time. The silicon-carbon Si1-yC y, material is pseudomorphically grown by selective epitaxy and the carbon mole fraction y incorporated is 1%. Si0.99C 0.01 S/D was employed to induce uniaxial tensile...
Reliability properties of bandgap engineered SONOS (BE-SONOS) (Lue et al., 2005) are extensively studied. First, the erase mechanism of BE-SONOS is confirmed as substrate hole tunneling through the ultra-thin ONO tunneling dielectric. Next, very long-term (>3,000 hours) high-temperature baking data (from 150 to 250degC) for various programmed/erased states and cycling history are collected and...
We have successfully manufactured a large-area power transmission sheet by using printing technologies. The position of electronic objects on this sheet can be contactlessly sensed by electromagnetic coupling using an organic transistor active matrix. Power is selectively fed to the objects by an electromagnetic field using a plastic MEMS-switching matrix
Extraction of the intrinsic NBTI degradation rate in the high-k pMOSFETs was found to require correction of the measured threshold voltage shift (DeltaVTH) for the fast transient charging contribution caused by the charge trapping in pre-existing defects in high-k films. The proposed analysis methodology leads to a significantly lower estimated lifetime than that obtained by the generally used approach...
Program/erase cycling stress induced read current fluctuations arising from random telegraph noise (RTN) in a localized storage, multi-level nitride flash memory (SONOS) is explored. Our study shows that localized charge storage significantly enhances RTN. The amplitude of RTN varies in different program levels of a multi-level cell. The broadening of read current distribution due to RTN is characterized...
We report performance optimization techniques for FinFETs with Si 0.99C0.01 source and drain (S/D) regions and sub-30 nm gate lengths. By scaling up the Si0.99C0.01 stressor thickness, a ~9% IDsat enhancement can be obtained. A further 16% IDsat enhancement can be achieved with the adoption of slim spacers. Carrier backscattering study was performed to clarify the carrier transport characteristics...
We investigate the properties of traps in the SiO2 by means of a statistical analysis of random telegraph noise in Flash memory arrays. We develop a new physical model for the statistical superposition of the elementary Markov processes describing traps occupancy, able to explain the experimental evidence for cell threshold voltage instability. Comparing modeling results with experimental data allowed...
A threshold voltage fluctuation (?Vth) due to random telegraph signal (RTS) in a floating-gate (FG) flash memory was investigated. From statistical analysis of the ?Vth, we found an anomalously large ?Vth at high percentage region of the ?Vth distribution, which is caused by a complex RTS. Since the ratio of the complex RTS among the RTS is increased by charge injection to tunnel oxide, the dispersion...
High performance LSTP CMISFETs with poly-Si/TiN hybrid gate and high-k dielectric have been studied. Gate depletion is successfully suppressed by in-situ phosphorus doped poly-Si gate for NMIS and by TiN metal gate for PMIS. Vth control for pMIS is accomplished by fluorine implantation into substrate. Optimization of HfSiON formation and TiN removal process is the key to achieve high-reliability....
The authors have demonstrated the stacked MOCVD HfSiON gate dielectrics with extremely low Hf concentration (Hf/(Hf+Si)=6%) cap (LHC) which realized improved mobility and superior long-term reliability of CMOSFETs while maintaining low gate leakage currents and EOT scalability to 1nm. These superior electrical characteristics of the film are mainly owing to the suppression of the Vo2+ formation in...
We show for the first time that control of the crystalline phases of HfO2 by tetravalent (Si) and trivalent (Y,Gd) dopants enables significant improvements in the capacitance equivalent thickness (CET) and leakage current in capacitors targeting deep trench (DT) DRAM applications. By applying these findings, we present a MIM capacitor meeting the requirements of the 40 nm node. A CET < 1.3 nm was...
This paper describes a novel RF CMOS-MEMS switch that integrates RF MEMS switches and CMOS control circuits. A single-pole 8-through RF CMOS-MEMS switch was fabricated and its operation at 3.3 V supply voltage was achieved. The switch was encapsulated with a thin film at wafer level to prevent destruction during packaging. Experimental results confirm that the switch has mechanical reliability for...
Spacer-defined fin-patterning results in double/quadruple fin density and hence is attractive for high performance 32-nm CMOS applications. For the first time 55-nm gate-length FinFET SRAMs with resist- and spacer-defined fins are electrically compared. Due to short-range process variations, SRAM bit-cells with spacer-defined fins show approximately 2.5 times higher variability in static-noise-margin...
The authors present a 65nm embedded DRAM cell (0.127 μm2 cell size) on unpatterned SOI fabricated using standard high performance SOI technology with dual stress liner (DSL). The cell utilizes a low-leakage 2.2-nm gate oxide pass transistor and a deep trench capacitor. A trench side wall spacer process enables a simplified collarless process. Connection to the buried plate is realized by silicided...
A novel orthogonal wiggle cell for either adjacent-reference architecture or self-reference architecture is proposed to enhance the read/write operation of MRAM. With reliability and non-disturbance of the device being verified, the mass production of MRAM is feasible because of the stabilized functionality and improved performance
We developed novel SRAM cells using bulk thyristor-RAM (BT-RAM). BT-RAM, formed on bulk Si wafers, is low cost and has good compatibility with logic process flows. BT-RAM has excellent performance, with a 100-ps read/write, high Ion/Ioff current ratio (> 108), and low standby current (< 0.5 nA/cell). We can expect the ideal cell size to be as low as 30 F2, one-fourth that of a conventional 6T-SRAM...
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