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We present an advanced CMOS integration scheme based on embedded SiGe (eSiGe) with a novel graded germanium process. The retention of channel strain enabled a pFET performance gain of 15% over a non-graded eSiGe control. When combined with a compressive stress liner (CSL), the pFET drive current reached 770muA/mum at Ioff = 100nA/mum with VDD = 1V. Competitive nFET performance was maintained. Parasitics...
A study was performed to investigate the effect of multiple stressors on CMOS devices on (110) and (100) substrates with different channel directions. For the first time, 87% ION-IOFF improvement is achieved by utilizing SiGe-S/D and compressive contact etch stop layer (c-CESL) for PMOS devices on (110) substrate with lang111'rang channel direction. The improvement is similar to that on conventional...
Low temperature device operation at 240 - 300 K temperature range is a promising approach to extend the device technology. The guideline of device design for cooling CMOS and the optimum operation temperature considering total power consumption is discussed for the first time. Also, the compatibility of cooling CMOS with advanced high-k gate dielectrics and embedded SiGe S/D technique are clarified
A novel method for realizing arrays of vertically stacked (e.g., times3 wires stacked) laterally spread out nanowires is presented for the first time using a fully Si-CMOS compatible process. The gate-all-around (GAA) MOSFET devices using these nanowire arrays show excellent performance in terms of near ideal sub-threshold slope (<70 mV/dec), high Ion/Ioff ratio (~107), and low leakage current...
A novel strained-SiGe n-channel field-effect transistor (nFET) featuring silicon-carbon (Si0.99C0.01) source/drain (S/D) stressors and tensile stress nitride (SiN) liner is demonstrated for the first time. The silicon-carbon Si1-yC y, material is pseudomorphically grown by selective epitaxy and the carbon mole fraction y incorporated is 1%. Si0.99C 0.01 S/D was employed to induce uniaxial tensile...
The interaction of epitaxially strained SiGe and super annealing or millisecond anneal in high performance PFET fabrication was, for the first time, systematically investigated. When super annealing was applied, the quality of SiGe/Si interface, affected by subsequent ion implantation and post-SiGe thermal treatment, played an important role in SiGe strain relaxation incurring channel stress loss...
The impact of defects on the short channel effects (SCE) and the drivability of a pMOSFET with a SiGe source/drain is described, and useful methods to reduce defect formation are suggested. The influence of defects on device performance is found to become more severe as recess depth increases and/or channel length decreases. By optimizing the epitaxial process, including an in-situ precleaning step,...
We present a 45-nm SOI CMOS technology that features: i) aggressive ground-rule (GR) scaling enabled by 1.2NA/193nm immersion lithography, ii) high-performance FET response enabled by the integration of multiple advanced strain and activation techniques, iii) a functional SRAM with cell size of 0.37mum2, and iv) a porous low-k (k=2.4) dielectric for minimized back-end wiring delay. The list of FET-specific...
The authors demonstrate a low-cost, high-performance, high-voltage complementary SiGe:C BiCMOS process. This technology offers three npn SiGe:C devices with fT/BVCEO values of 40GHz/5V, 63GHz/3.5V, and 120GHz/2.1V together with a 32GHz fT/35GHz f max/ 4.4V pnp SiGe:C HBT by adding only three bipolar masks to the underlying RF-CMOS process. With two additional implant masks, a 150GHz, 2.2V npn HBT...
A new negative differential resistance (NDR) effect is reported for the first time in cryogenically-operated SiGe HBTs. A physical explanation based on heterojunction barrier effect (HBE) is presented, and confirmed using calibrated 2-D TCAD simulations. The ac consequences of this NDR effect and the impact of technology scaling on the phenomenon are also addressed
Mobility and strain mechanisms of SiGe channel pMOSFETs fabricated with <110> channel direction on (110) Si substrate (<110>/(110) SiGe channel) have been studied in details for the first time. The combination of substrate orientation, high mobility channel material and extrinsic stained-Si process demonstrates the ultra high mobility enhancement and results in 80% current gain. The piezoresistance...
A novel device structure containing a SiGe stressor is used to impose tensile strain in nMOSFET channel. 400MPa of uniaxial tensile stress is induced in the Si channel through elastic relaxation/strain of the SiGe/Si bi-layer structure. This strain results in 40% mobility enhancement and 15% drive current improvement for sub-60nm devices compared to the control device with no strain
Using the non-local empirical pseudopotential method (bandstructure), full-band Monte-Carlo simulations (transport), 1D Poisson-Schrodinger (electrostatics) and detailed band-to-band-tunneling (BTBT) (including bandstructure and quantum effects) simulations, the effect of uniaxial- and biaxial-strain, band-structure, mobility, effective masses, density of states, channel orientation and high-field...
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