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The "silicon on nothing" (SON) technology (Jurczak et al., 1999) and (Jurczak et al., 2000) is a promising candidate for the end-of-roadmap CMOS. In this paper we present the SON technology, show examples of sustained mono-Si nano-membranes over an empty tunnel, and deliberate on the suitability of this kind of 3-D nano-structures to build-up electronic devices. This technology opens a wide...
The scaling of CMOS transistors is discussed from the perspective of the 2005 International Technology Roadmap for Semiconductors. Numerous critical scaling challenges are identified, including excessive gate leakage current, difficulty in controlling short-channel effects, need for enhanced mobility, and others. To deal with these, numerous major technological innovations will be required, such as...
Future trends are discussed of the semiconductor mainstream technology in the next 1 1/2-decade towards the "scaling end" of the ITRS Roadmap and beyond. While the physics, design, and manufacturing limitations of CMOS scaling will be indisputably strike in the foreseeable future, emerging nanotechnology may step in to promote continued advancement of chip technology in terms of performance,...
Sub-10nm CMOS devices are the critical issue, because CMOS scaling is going to be sub-25nm regime. Scaling issues of nano-size MOSFETs can be discussed on the basis of sub-10 nm MOSFETs characteristics, which have been developed and confirmed switching characteristics and low-temperature characteristics. Studying device limitation issues and developing new breakthrough technologies are required to...
An overview of critical integration issues for future generation MOSFETs towards 10 nm gate length is presented. Novel materials and innovative structures are discussed. The need for high-K gate dielectrics and a metal gate electrode is discussed. Different techniques for strain-enhanced mobility are discussed
Recent results on the characterization and applications of the SOI four-gate transistor (G4-FET) are reviewed. The advantages provided by four independent gates are discussed by distinguishing different operation modes: volume (depletion-all-around) and surface conduction. Several examples highlight the potential of the G4-FET for analog applications
In this paper, we assess the potential for bulk CMOS, SOI CMOS, and double-gate CMOS to extend scaling to 10 nm channel length. In addition to the required replacement of silicon dioxide and polysilicon gates by high-k insulator and metal gates for all device types, specific technology requirements are discussed for each device type. 10 nm bulk CMOS requires abrupt placement of n- and p-type dopants...
We explore technology options for the enhancement of electron mobility in n-FETs, focusing on channel strain engineering using lattice-mismatched source/drain (S/D) materials. By employing silicon-carbon (Si1-yCy) in the S/D regions, lateral tensile strain in the Si channel is induced for electron mobility and drive current IDsat improvement. Further performance enhancement is achieved by the combination...
In this paper, a novel Schottky tunneling source MOSFET utilizing the concept of gate controlled Schottky barrier tunneling has been examined and successfully demonstrated. Much better short channel immunity in terms of smaller DIBL, reduced threshold roll-off and increased output resistance has been confirmed. Excellent ROUT and gain as compared to conventional SOI-FET are demonstrated. To further...
Among emerging issues on nanoscale MOSFETs, two aspects are discussed. One is a new type of parasitic capacitance in MOS capacitors, and the other is analysis of channel transport in terms of a newly developed reflection-transmission formalism. The non-zero thickness of charge layer in the MOS gate electrode causes a new type of parasitic capacitance, which is comparable to and is equally serious...
Since the end of the last millenium, the microelectronics industry is facing new issues as far as CMOS devices scaling is concerned. Linear scaling will be possible in the future if new materials are introduced in CMOS devices structure or if new devices architectures are implemented. The demand for low voltage, low power and high performance are the great challenges for the engineering of sub 50nm...
The 2005 International Technology Roadmap for Semiconductors predicts a printed minimum MOS-transistor channel length of 9 nm for the year 2020, which results in a physical gate length of only 6 nm. The resolution of optical lithography still dramatically increases, but known and proved solutions for structure sizes significantly below 50 nm do not exist until now. Above these dimensions the known...
In this paper, the temperature impact on the Lorentzian noise induced by electron valence band tunneling (EVB) is analyzed for partially depleted SOI MOSFETs. In (Lukyanchikova et al., 2003) and (Lukyanchikova et al., 2004) the Lorentzian noise parameters were already studied at 300K and a model based on shot noise of the EVB tunneling current was proposed. The aim of this paper is to investigate...
This paper is submitted with an investigation concerning the effects of the Si thickness-induced variation of the electrical characteristics in the FDSOI with block oxide. We noticed that the traditional sidewall spacer process is used and processed to produce the block oxide enclosing the Si-body in our proposed structure, the undesirable ultra-short-channel effects can be significantly diminished...
Improved mobility and low flicker noise device characteristics of fully depleted silicon-on-insulator (FD-SOI) MOSFETs are focused in this paper, using normally off accumulation mode device structures. It is demonstrated that the current drivabilities of both accumulation mode FD-SOI n-and p-MOSFETs are improved above 1.3 times compared with inversion mode MOSFETs. The effective mobilities of accumulation...
We are trying to submit with this paper a new concept concerning the partial silicon-on-insulator (SOI) process, aiming to fabricate the self-aligned pseudo-SOI device structures - (a) the silicon on partial insulator with block oxide FET (bSPIFET), and (b) the partially insulating oxide (PiOX) under source/drain (S/D) (PUSD) partially insulated field-effect transistor (PUSD PiFET) (Yeo et al., 2004)...
The mechanism responsible for the short-channel electron mobility (e$mobility) abnormal degradation in n-type tall fins multiple-gate field-effect transistors (MuGFETs) has been identified. RF-CV measurement, mobility extraction, and 1/f noise measurements have been performed and point to a larger process related density of traps (N t) at the gate edges. These traps and their distribution along the...
For the first time, partially-depleted silicon-on-insulator (PDSOI) accumulation-mode dynamic threshold (AMDT) pMOS with TiSi2 /n-Si as reverse Schottky barrier (RSB) is reported. By this RSB scheme, AMDT pMOS can be operated beyond 0.7 V, which is the drawback of conventional DT pMOS with gate and body connected (GBC). Compared with normal AM pMOS, AMDT pMOS with RSB reduces threshold voltage by...
This paper describes TSNWFET devices with embedded Si1-xGex source/drain regions and different nanowire orientations. Thick Si1-xGex embedded source/drain and lang110rang channel orientation is found effective to enhance p-channel TSNWFET performance, while cause degradation for n-channel one. Thin Si1-xGex and lang100rang channel orientation is the preferred combination for keeping n-TSNWFET performance...
We demonstrate multi-bridge-channel MOSFET (MBCFET) with new gate structure on bulk Si wafer. Sub 25nm MBCFET shows excellent transistor characteristics, such as 750,000 times on/off current ratio and 3.61mA/mum drive current at 4.8nA/mum of off-state current by using tall-embedded-gate (TEG) structure. And thanks to suitable threshold voltage for n,pMBCFET and high current drivability, we successfully...
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