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The minimization problem of an L2-sensitivity measure subject to L2-scaling constraints on the dynamic range for multi-input/multi-output (MIMO) linear discrete-time systems is formulated. An iterative technique is developed to solve the constrained optimization problem directly. The proposed solution method largely relies on the use of a Lagrange function and some matrix-theoretic techniques. A numerical...
In this paper, the problematic of co-design between LNA and antenna is addressed. The targeted application is ultra wide band where this part of front end is a main interest in RF design. A comparison is drawn out between a 50 Ohm and a co-designed version, with same LNA architecture and power consumption. Simulation results show a 7 dB power gain enhancement in the latter version. Noise factor is...
A CMOS low noise amplifier (LNA) is proposed for a proof-of-concept design of the square kilometer array (SKA) radio telescope. A novel variation on a well-known source-degenerated LNA topology is introduced that allows tuning of the power match centre frequency independently from the frequency at which the LNAs noise figure approaches its minimum noise. The 0.7-1.4 GHz LNA designed in 0.18mum CMOS...
This paper presents a novel intrabody communication system, in which the base-band signal is directly transmitted through human body and electrically recovered, and its architecture are. The electrical characteristics of the human body in terms of a communicational channel are investigated from 1KHz to 10MHz using the equipment with a floating ground. The signal from universal asynchronous receiver...
We present a silicon neuron that uses shunting inhibition (conductance-based) with a synaptic rise-time to achieve synchrony. Synaptic rise-time promotes synchrony by delaying the effect of inhibition, providing an opportune period for neurons to spike together. And shunting inhibition, through its voltage dependence, inhibits neurons that are late more strongly (delaying the spike further), thereby...
A low power, high bandwidth continuous-time delta-sigma modulator is proposed in this paper. In contrast to traditional continuous-time delta-sigma modulators, this design utilizes passive networks, consisting of only resistors and capacitors, to perform part of the functions of loop filters. Passive networks do not consume power, introduce no distortions. For similar performance, considerable power...
A CMOS-compatible one-time programmable (OTP) memory array for RFID applications is presented. Three zero-mask antifuse (AF) devices were evaluated on their feasibility for RFID applications. Among the AFs, the gate oxide AF device can be programmed using only 7 muW of peak power and was chosen to form the RFID memory array. A memory array architecture is presented based on a compact 2-transistor...
A novel AND-type match-line scheme with XOR-based conditional keeper for ternary content-addressable memory (TCAM) are presented in this paper. The XOR-based conditional keeper is turned off at some critical moments to reduce the search time and power consumption. High fan-in AND-type match-line schemes are used to demonstrate the effectiveness of the XOR-based conditional keeper in the presence of...
An analytical method for power supply spectrum estimation to be used in early system planning is proposed. The method is based on a careful evaluation of a number of parameters of an equivalent inverter; rise time, fall time and widths of current impulses. We assume an inverter to be a basic building component of digital blocks. Using the proposed method one can determine estimates of power supply...
With the continued scaling of feature sizes in deep submicron technology, on-chip interconnects have become a dominant factor affecting performance and reliability in high performance integrated circuits (IC). The longer on-chip interconnects coupled with a decrease in wire width and wire separation, inductive effects, and more specifically, mutual inductance coupling between neighbouring wires become...
Because SOC (system-on-a-chip) needs multiple clocks and mostly with 50% duty cycle in same chip. We use multiphase outputs of voltage-controlled oscillator (VCO) in a phase-locked loop (PLL) to generate the needed frequencies with 50% duty cycle. Further, we propose a design flowchart to solve the problem of pseudo fractional-N clock generator. The circuits are processed in a standard 0.13mum CMOS...
Vulnerability of combinational logic to soft errors exponentially increases with technology scaling. Reducing soft error susceptibility of logic gates comes with extra area, delay, and power consumption overhead that needs to be balanced in the entire circuit. In this paper, we present efficient soft error hardening techniques based on selective gate resizing to maximize soft error suppression for...
The paper considers a large class of additive neural networks where the neuron activations are modeled by discontinuous functions or by non-Lipschitz functions. A result is established guaranteeing that the state solutions and output solutions of the neural network are globally convergent in finite time toward a unique equilibrium point. The obtained result, which generalizes previous results on convergence...
Several options are available for the approximating of color images in hardware, both in terms of the type of transformation (e.g., quantization, dithering) as well as in terms of where the approximation takes place (e.g., graphics controller, frame buffer, LCD controller). In this work, we propose a color approximation approach, orthogonal to other color simplification schemes, which is done during...
Low-k dielectrics will be required to continue miniaturisation of integrated circuits beyond the 90 nm node. The integration of these advanced materials results in significant reduction of signal delay and power dissipation compared to conventional silicon dioxide. As the technology continues to advance, the implementation of low-k dielectrics for the 65 nm node (Luo, et al., 2004) causes also problems,...
Although current-programmed pixel circuits lead to a highly stable amorphous silicon (a-Si) active matrix backplane, they are prone to a long settling time due to the large parasitic capacitance coupled with the low mobility of a-Si thin film transistors (TFTs). This paper presents a fast-current source that can significantly improve the settling time of the a-Si active matrix. Also, to reduce the...
A significant part of the energy consumed by a flat panel display is dissipated in the controlling circuitry. The column line flat panel display driver proposed in (Saas et al., 2004) has shown the high potential of stepwise charging to reduce the power dissipation while driving the column lines of the display. The driver has been extended to full dynamic resolution in (Saas et al., 2005), thus allowing...
A SIMD processor that contains a 16-way partitioned data-path is designed for efficient multimedia data processing. In order to automatically align data needed for SIMD processing, the architecture adopts a vector memory unit that consists of 17-bank memory blocks. The vector memory unit also has address generation and rearrangement units for eliminating bank conflicts. The MicroBlaze FPGA based RISC...
Routing FPGAs (Verma, 1999) is a challenging problem because of the relative scarcity of routing resources represented in wires and connection points. This can lead either to slow implementations caused by long wiring paths that avoid congestion or a failure to route all signals (McMurchie, 1995). This paper presents some enhancements to improve both the performance and routability of the routability-driven...
This paper presents a very low area design for the advanced encryption standard (AES) capable of functioning in three of its feedback modes to provide flexible support for its use as a stream cipher. The architecture is based around an 8-bit application specific instruction processor (ASIP) and includes UARTs to support asynchronous serial I/O. The entire design fits within the smallest Xilinx Spartan-II...
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