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We explore the 6T and 8T SRAM design spaces through read static noise margin (RSNM), word-line write margin, and leakage for future 10-nm FinFETs. Process variations are based on the ITRS and modeled at device (TCAD) level. We propose a method to incorporate them into a BSIM-CMG model card for time-efficient simulation. We analyze cells with different fin numbers, supply voltages, and temperatures...
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