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This presentation will highlight some of the challenges and opportunities that test developers and test operations managers face in a changing data climate. Measured data will drive decisions not only about the product under test, but potentially on the entire design and manufacturing ecosystem. I will also explore some of the value tradeoffs of increased data harvesting vs. reduced test cost requirements...
The ITC'97 analog and mixed-signal (A/MS) benchmark circuits have been available for two decades. This paper discusses why they were useful but not for comparing A/MS design-for-test (DFT) techniques, tests, or fault coverage. First, this paper discusses these and other benchmark circuits, and proposes objectives for better benchmark circuits. The paper then describes the first, publicly-available...
To ensure robustness of integrated systems, the TRAnsition-X (TRAX) fault model has been used with on-chip test and diagnosis hardware, utilizing fault dictionaries for diagnosis. Generating a fault dictionary requires fault simulation with no fault dropping, requiring extensive computational resources. This paper presents the design and implementation of an efficient fault simulator for the TRAX...
Due to technology scaling, which means smaller transistor, lower voltage and more aggressive clock frequency, VLSI devices are becoming more susceptible against soft errors. Especially for those devices deployed in safety- and mission-critical applications, dependability and reliability are becoming increasingly important constraints during the development of system on/around them. Other phenomena...
Analog-to-Digital Converters (ADCs) are becoming increasingly common to be involved in most systems in Integrated Circuits (ICs). Thanks to the rapid growth of modern semiconductor technology, the performance of the data converters becomes better and better. One of the difficulties being faced is to be able to accurately and cost-effectively test the continually better performance ADCs. The conventional...
A contemporary high-performance system board is a complex 3D object that may contain dozens of hidden layers, stacked microvias, high density interconnect, with all of the above not contributing to the ease of test and reliability. High-speed signals are normally fine-tuned or even calibrated to deliver pitch perfect timing even in the case of now-ubiquitous DDR3 memories. Today, data transmission...
Many analog and mixed signal devices have very few or no digital pins. In spite of this, these products can be highly complex internally, including significant digital content. They may contain various sensors and control circuitry, which react to a variety of conditions to control the power profile of the part and its environment. These factors can make these devices very challenging to test. They...
With wafer fabs running at near full capacity, it is a constant challenge to maintain high yields. Many different products are fabricated by the same equipment. So the sudden change in product yield, a yield excursion, can have a significant impact to many different products. Therefore, it is critical to detect an excursion as early as possible and fix the cause in order to minimize the impact. This...
IOT has seen countless potential applications that can improve our lives dramatically, but after years of efforts by numerous companies and organizations, the beautiful dreams are yet to be realized. The main obstacles are cost and energy consumption constraints of the devices and systems, which still cannot be contained. As a step forward in improving the reliability and reducing the cost and energy...
This paper presents a built-in self-test (BIST) system for Low-Dropout Regulators (LDO). Since the LDO is a closed-loop system, stability is a very important but oft-untested parameter for embedded LDOs. The proposed BIST system can measure stability-related parameters by performing cross correlation between an input pattern mimicking noise in the form of Pseudo Random Binary Sequence (PRBS) and the...
This paper presents a novel low-area scan-based logic built-in self-test (LBIST) scheme that addresses stringent test requirements of certain application domains such as the fast-growing automotive electronics market. These requirements, largely driven by safety standards, are met by significantly reducing test application time while preserving the high fault coverage of conventional BIST schemes...
The number of on-chip embedded instruments required for testing, debugging, and monitoring integrated circuits (ICs) has increased dramatically. The IEEE 1687 (IJTAG) standard can allow efficient access to these embedded instruments by dynamically reconfiguring the scan chain using Segment Insertion Bits (SIBs). Unfortunately, instruments that require a large amount of test data and several accesses...
Online testing is critical to ensure reliable operation of manycore systems based on a network-on-chip (NoC) interconnection fabric. We present a software-based online NoC self-testing solution based on bounded model checking (BMC). The proposed method first implements BMC on a sliced extended finite-state machine, and extracts the leading sequences necessary to excite NoC functions. Next, it targets...
Test Compression ratios are currently stalled at 100–200X. A new 2-dimensional physically-aware sequential Compressor-Decompressor design addresses the severe wiring congestion as well as the test coverage droop and pattern spike at the highest compression ratios. Results on some commonly used industrial designs shows a 2X reduction in routing overhead and congestion associated with Test Compression...
Future 5G wireless systems will deploy massive MIMO systems with large numbers of transmit and receive antennas and novel RF transceiver architectures that admit RF beamforming. Such systems will need to be designed with built-in test and post-manufacture self-tuning capability for yield enhancement and in-field tuning. A key issue is the lack of observability into internal circuit nodes due to the...
Outlier screening is a popular approach employed for automotive product lines. There have been many outlier methods proposed. In practice, it is desirable to choose the “best” outlier method. This work develops a notion of applicability associated with an outlier method on a given set of wafers. A measure for applicability is proposed and experiment results are presented to illustrate its effects...
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