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3D VLSI with a CoolCube™ integration allows vertically stacking several layers of devices with a unique connecting via density above a million/mm2. This results in increased density with no extra cost associated to transistor scaling, while benefiting from gains in power and performance thanks to wire-length reduction. CoolCube™ technology leads to high performance top transistors with Thermal Budgets...
The further growth of billions of wirelessly connected devices requires a technology infrastructure that can handle a massive increase in storage, computing power and bandwidth, some of it available via cloud computing, to enable number crunching at very large scale and at high volume, low cost and low power. The IoT applications or ‘smart devices’ require the following technology enablers: ultra-low...
A non-volatile programmable logic (NPL) with atom switch significantly accelerates performance of micro-controller unit. A low-power 32bit-CPU using a 65 nm-node Silicon-on-Thin-Box (SOTB) CMOS performs 1.95 DMIPS/MHz and 33 µW/MHz on 25 MHz and VDD=0.4V. When a software process in the CPU is offloaded to NPL, the 9 times faster processing speed and 3 times higher energy efficiency are realized. A...
This study proposes a 7T1R nonvolatile SRAM (nvSRAM) to 1) reduce store energy by using a single NVM device, 2) suppress DC-short current during restore operations through the use of a pulsed-overwrite (POW) scheme, and 3) achieves high restore yield by using a differentially supplied initialization (DSI) scheme. This initialization-and-overwrite (IOW) 7T1R nvSRAM improves breakeven-time (BET) by...
This paper presents the first energy efficient highly compact concept of active pixel sensor built with a single partially-gated tunnel FET (TFET). Experimental results show that the transistor characteristics of the investigated TFETs are nonlinearly modulated by optical excitation and a transistor gain that is a function of irradiance and bias conditions is reported for the first time. A memory...
In0.53Ga0.47As channel MOSFETs were fabricated on 300 mm Si substrate. The epitaxial In0.53Ga0.47As channel layer exhibits high Hall electron mobility comparable to those grown on lattice matched InP substrates. Excellent device characteristics (SS∼95 mV/dec., Ion/Ioff ∼105, DIBL ∼51 mV/V at Vds = 0.5V for Lg=150 nm device) with good uniformity across the wafer were demonstrated. The extracted high...
For 28-nm embedded application, we have proposed a TaOx-based ReRAM with precise filament positioning and high thermal stability. The cell was realized using several newly-developed process technologies and cell structures: low-damage etching, cell side oxidation and encapsulated cell structure. As a result, we succeeded for the first time in forming a filament at the cell center. In addition, we...
We have shown a practical device design guideline for sub-0.2V ultra-low power, steep slope ferroelectric FET using negative capacitance (NC) focusing on operation speed, material requirement, and energy efficiency for the first time. The operation speed is determined by finite switching time of ferroelectric polarization. For low supply voltage and hysteresis-free design, there exists a ferroelectric...
Random variation of threshold voltage (Vt) in MOSFETs plays a central role in determining the minimum operating voltage of products in a given process technology. Properly characterizing Vt variation requires a large volume of measurements of minimum size devices to understand the high sigma behavior. At the same time, a rapid measurement approach is required to keep the total measurement time practical...
In this work, we have experimentally demonstrated for the first time, an Analog-to-Digital Converter (ADC) based on the unique voltage-dependent switching probability of a Magnetic Tunnel Junction (MTJ). The switching probability was calculated by applying repetitive voltage pulses and measuring the resolved MTJ states in each sampling time window. Temperature sensitivity and MgO breakdown issues...
This paper presents a three-dimensional (3D) fully integrated high-speed multiphase voltage regulator. A complete switched-inductor regulator is integrated with a four-plane NoC in a two-high chip stack combining integrated magnetics, through-silicon vias (TSVs), and 45-nm SOI CMOS devices. Quasi-V2 hysteretic control is implemented over eight injection-locked fixed-frequency phases to achieve fast...
We systematically investigated the impact of R and C scaling to 7nm node (N7) by accounting for FEOL and BEOL holistically. Speed-power performance of plainly scaled N7 turns out to be degraded compared to previous node. BEOL wire resistance (Rwire) multiplied by logic gate input pin cap (Cpin), Rwire×Cpin, is identified as a major limiter of performance and power at N7. Reducing Cpin is crucial to...
Internet and mobile application have been the driving force for semiconductor innovation in the past 10 years. In this paper, we will focus on the system requirement for today's and tomorrow's consumer gadgets from productivity laptop computers to wearable glasses or watches. We will start with everyone's favorite activity such as taking pictures and sharing with friends, listening to the YouTube...
We demonstrate single- and double-gated (SG & DG) field effect transistors (FETs) with a record source-drain length (LS/D) of 15 nm built on monolayer (tch∼0.7 nm) and 4-layer (tch∼3 nm) MoS2 channels using monolayer graphene as the Source/Drain contacts. The best devices, corresponding to DG 4-layer MoS2-FETs with LS/D=15 nm, had an Ion/Ioff in excess of 106 and a minimum subthreshold swing (SS...
The effect of random telegraph noise (RTN) on write stability of SRAM cells in sub-0.4V operation is intensively measured and statistically analyzed. RTN of N-curves in Silicon-on-Thin-BOX (SOTB) cells is monitored. By developing statistical models, it is found that, different from bulk SRAM cells operating at high supply voltage (VDD), fail bit rate (FBR) at sub-0.4V is degraded by RTN. The origin...
The tunneling FET (TFET) is a leading option for energy efficient computation with peak logic performance/watt greater than CMOS. With variation effects, TFET reaches 2X higher peak efficiency than MOSFET by using supply voltages under 0.4V. Dense TFET SRAM bitcell is proposed with VMIN matching this low logic VDD. Projections of device variation enable a comparison of TFET and MOSFET logic and memory...
In the overwhelming majority of cases, current-voltage characteristics of metal-based contacts on semiconductors are non-linear around 0V even for degenerate interfacial doping levels. Any contact resistivity specification is therefore meaningless without the knowledge of the effective bias across the contact. For the first time, the efficiency of a dielectric insertion for contact resistance reduction...
Endurance and retention are measured in 1Xnm Triple Level Cell (TLC) NAND and the flexible nLC scheme (flex-nLC) is proposed to improve reliability. This method enables the use of lowest-cost TLC NAND as is, in long term storage applications such as cold flash and digital archive: millennium memory, which have 20 and 1000 years retention, respectively.
Enabling a high-density ReRAM product requires: developing a cell that meets a stringent bit error rate, BER, at low program current, integrating the cell without material damage, and providing a high-drive selector at scaled nodes. We discuss ReRAM performance under these constraints and present a 16Gb, 27nm ReRAM capable of 105 cycles with BER < 7×10−5.
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