The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Measurements of the I(V) characteristic in Ovonic semiconductors are notoriously unstable. Experimental setups must therefore rely on pulsed schemes in which only the positive-slope branches of the characteristic are detected. This paper considers the time-dependent, trap-limited conduction model proposed by the authors for investigating this type of devices, and shows that the model is suitable for...
The electron spin properties of semiconductors are of huge interest because of their potential for future spin-driven microelectronic devices. Modern charge-based electronics is dominated by silicon, and understanding the details of spin propagation in silicon structures is key for novel spin-based device applications. The peculiarities of the subband structure and details of the spin propagation...
This paper presents an experimental analysis of the high temperature influence on the main digital and analog parameters in triple gate nFinFET devices processed on both Bulk and Silicon-On-Insulator (SOI) substrates. Regarding the studied analog parameters, there was no significant variation as the temperature increases, at least for the temperature from 25°C to 150°C. Moreover, the SOI FinFET (SFF)...
This work develops an analytical model which correlates the changes of the threshold voltages in Pseudo-MOSFET structures with the charge intentionally placed on the surface of the native oxide. The model has been validated through experimental I-V characteristics obtained when the surface is physically altered with an APTES solution. The measurements were performed in 15 MESA isolated SOI cells....
This work focuses on the high temperature analysis in extensionless ultra-thin body and buried oxide (UTBB) SOI MOSFETs in dynamic threshold (DT) mode, as well as in enhanced DT (eDT) mode operation for the first time. In spite of the higher transconductance temperature degradation factor (c), the DT and eDT operations resulted in a lower VT variation with temperature and a lower Zero-Temperature-Coefficient...
Reverse terrace graded (RTG) Si1−xGex/Ge relaxed buffer layers grown on Si(001) substrates that are oriented on-axis and off-axis (6° toward the [110] direction) show similar levels of strain, surface roughness and threading dislocation density (TDD) to Ge and Si1−xGex epilayers of similar thickness and Ge content. For identical growth conditions and times, a reduced growth rate is observed for buffer...
This paper presents results introducing a novel method of fabrication of thin silicon films based on combination of film separation by Smart Cut™ technology and a high temperature liquid phase epitaxy. The separation kinetics of the substrate is characterized for silicon, implanted with a dose of 5.0×1016 H×cm−2 and an implantation energy of 60 keV, over a range of temperature from 450°C to 700°C...
We report the first demonstration of ultrathin-body GeOI MOSFETs utilizing a surface region of Smart-Cut™ GeOI substrates with high material quality. The devices are realized by flipping the Smart-Cut™ GeOI substrates, directly bonding them to another Si substrate, removing the supporting Si substrate of the Smart-Cut™ GeOI and thinning the flipped GeOI films. The normal operation of pMOSFETs is confirmed...
The effects of electrical stress and ionizing radiation on the characteristics of Si-based TFETs were investigated experimentally. We found that the electrical stress effects in TFETs could not be ignored in radiation tests, since they can possibly overwhelm the radiation-induced degradation. Under this circumstance, a lower gate voltage under which the electrical stress effects were suppressed induced...
DRAM capacitors are reaching the scaling limit and new approaches are necessary to enable further reduction of the physical thickness of the capacitor dielectric. The Schottky Barrier Height (SBH) of a noble metal electrode (Pt) on atomic layer deposited ZrO2/Al2O3/ZrO2 (ZAZ, 6 nm) was evaluated and compared to a TiN electrode. Internal Photo Emission Spectroscopy (IPE) and Photoconductivity measurement...
In this work, the static and low frequency noise characterization of standard and rotated UTBOX n — type transistors is reported. The main short channel effects and analog parameters are studied in order to investigate the impact of the channel orientation: <110> versus <100>. In addition to the improvement on the electrical properties for the rotated — channel devices, the 1/f noise level...
In this work a comparison of the analog performance between vertical silicon Nanowires Tunnel Field Effect Transistors (NW-TFETs) and nanowires MOSFETs (NW-MOSFETs) is performed mainly focusing on the basic analog characteristics at room and high temperatures for the first time. The opposite transconductance trend as a function of temperature and the much lower (better) output conductance obtained...
In this paper, the quantum confinement and short channel effects of Si, Ge, and In0.53Ga0.47As n-MOSFETs are evaluated using a quantum energy transport(QET) model based on Fermi-Dirac statistics. Both bulk and double-gate n-MOSFETs are simulated. The charge control by the gate is strongly reduced in In0.53Ga0.47As bulk n-MOSFETs due to low effective mass, high permittivity and high degeneracy material...
We present a self-consistent quantum simulation of an MoS2-WTe2 inter-layer Tunnel Field-Effect Transistor (TFET). Our calculations are based on the non-equilibrium Green's function (NEGF) formalism with electron-phonon scattering, and accurately account for the device electrostatics by a self-consistent coupling to the Poisson equation. Our results predict an extremely steep sub-threshold swing (SS<30mV/dec),...
Strained Si1−yCy epilayers with up to 1.48% C content have been grown on Si(001) by RP-CVD using the low-cost precursors disilane and trimethylsilane. These epilayers, with higher C content, were found to form point defects throughout growth resulting in amorphous hillocks forming on the epilayer surface. The size and density of these surface defects increases with C content and epilayer thickness...
We propose a Dynamically Biased Multi Threshold CMOS (DBMT) technique for power gating in FDSOI. In DBMT, effective threshold voltage of a high-Vt power switch transistor is lowered by forward body biasing (FBB) to improve performance at the operation, while it is raised by reverse body biasing (RBB) to further reduce leakage in the sleep state. We applied this technique to a 32-bit multiplier circuit...
A simple analytical model of thin-body In0.53Ga0.47As-on-InP MOSFET low-field electron mobility suitable for integration in Technology-CAD (TCAD) tools is presented. Phonon, Coulomb and surface roughness scattering are accounted for. In order to characterize the phonon scattering contribution, an expression for the device effective thickness is derived from 1-D Schroedinger-Poisson simulations. The...
As device dimensions are scaled down, the use of non-geometrical performance boosters becomes of special relevance. In this sense, strained channels are proposed for the 14 nm FDSOI node. However this option may introduce a new source of variability since strain distribution inside the channel is not uniform at such scales. In this work, a MSB-EMC study of different strain configurations including...
A TCAD-based approach has been used to investigate the leakage current and breakdown regime of vertical GaN/AlGaN/Si structures at different ambient temperatures. A good agreement with experimental data has been obtained by implementing both trap-assisted and Poole-Frenkel conduction mechanisms into the buffer layers. The latter mechanisms have been proven to anticipate the onset of breakdown at high...
Variability in graphene can result from the material synthesis or post-processing steps as well as the surrounding environment. This is a critical issue for the performance of large area devices as well as for the large-scale production of micro- and nano-scale graphene devices, leading to low yield and reliability. The aim of this study is to investigate variability of single and few-layer graphene...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.