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The aggressive scaling of NAND Flash memory technology — one that is even outpacing Moore's Law — has enabled very rapid cost-per-bit reduction, resulting in an explosion of systems utilizing this versatile memory technology. From removable media and personal music players to smart phones, tablets, and now personal computers and data center applications employing client and enterprise solid state...
Recently, mental diseases have been successfully treated by neuro-feedback therapy based on Quantitative EEG (QEEG) and Event Related Potential (ERP) online data measurements. The U.S. Food and Drug Administration (FDA) approved the first EEG test for diagnosing attention deficit hyperactivity disorder (ADHD) in 2013 [1]. The EEG signals are measured by an EEG cap and analyzed by a high performance...
As implantable medical CMOS devices become a reality [1], motion control of such implantable devices has become the next challenge in the advanced integrated micro-system domain. With integrated sensors and a controllable propulsion mechanism, a micro-system will be able to perform tumor scan, drug delivery, neuron stimulation, bio-test, etc, in a revolutionary way and with minimum injury. Such devices...
A very-long instruction word (VLIW) Hexagon™ DSP is fabricated using a 28nm high-κ metal-gate process technology optimized for mobile applications [1]. The DSP is designed for a heterogeneous computing environment. It targets high performance and low power across a wide variety of multimedia and modem applications, under aggressive area targets. Its architecture pursues high IPC as opposed to high...
Ultra-low-power (ULP) transceivers enable short-range networks of autonomous sensor nodes for wireless personal-area-network (WPAN) applications. RF PLLs for frequency synthesis and modulation consume a significant share of the total transceiver power, making sub-mW PLLs key to realize ULP WPAN radios. Compared to analog PLLs [1], all-digital PLLs (ADPLLs) are preferred in nanoscale CMOS as they offer...
The introduction of the IEEE802.15.6 standard (15.6) for wireless-body-area networks signals the advent of new medical applications, where various wireless nodes in, on or around a human body monitor vital signs. Radio communication often dominates the power consumption in the nodes, thus low-power transceivers are desired. Most state-of-the-art low-power transceivers support only proprietary modes...
Mobile time-keeping applications require small form-factor, tight frequency stability, and micro-power 32.768kHz clock references. Today's 32kHz quartz resonators and oscillators are facing challenges in size reduction [1,2]. Previously described MEMS-based oscillators can achieve tight accuracy but operate at high frequency with power unsuitable for mobile applications [3]. This paper introduces...
The 12-core 649mm2 POWER8™ leverages IBM's 22nm eDRAM SOI technology [1], and microarchitectural enhancements to deliver up to 2.5× the socket performance [2] of its 32nm predecessor, POWER7+™ [3]. POWER8 contains 4.2B transistors and 31.5μF of deep-trench decoupling capacitance. Three thin-oxide transistor Vts are used for power/performance tuning, and thick-oxide transistors enable high-voltage...
The demand for high-performance graphics capability even in extremely power-constrained platforms such as smartphones and tablets requires circuit techniques that scale from efficient operation at low voltage to high performance when needed. It is well known that energy efficiency improves as supply voltage is scaled down, reaching a maximum near the device threshold voltage where switching energy...
In high-performance microprocessor cores, the on-die supply voltage seen by the transistors is non-ideal and exhibits significant fluctuations. These supply fluctuations are caused by sudden changes in the current consumed by the microprocessor in response to variations in workloads. This non-ideal supply can cause performance degradation or functional failures. Therefore, a significant amount of...
A resonant-clock design for the IBM POWER8 processor core was implemented with 2 resonant modes (and a non-resonant mode), saving clock power over a wide frequency range from 2.5GHz to more than 5GHz. The POWER8 microprocessor is composed of 12 chiplets, each containing a single resonant clock grid for one core and its L2 cache, and a half-frequency, non-resonant clock grid for the L3 cache. The clock...
For an on-chip or fully integrated microprocessor power-delivery system, the on-chip power converter must 1) be designed using the same technology as the microprocessor, 2) deliver high power density to supply a microprocessor core with small area overhead, 3) achieve high efficiency, and 4) perform fast regulation over a wide voltage range for dynamic voltage and frequency scaling (DVFS). On-chip...
Potenza is a first generation 64b ARM v8 processor and memory sub-system of the X-GeneTM server platform [1]. The Potenza processor module (PMD) is an integrated design unit, comprising two identical cores sharing a 256KB L2 cache, and is designed to be scalable for different server configurations. Each PMD contains 84 million transistors, occupying over 14.8mm2, and averages 4.5W under representative...
Ultra-low-power (ULP), short-range wireless connectivity is becoming increasingly relevant to a wide range of sensor and actuator node applications, ranging from consumer lifestyle to medical applications. In recent years, a multitude of wireless standards has been proposed to meet differing requirements of individual application domains such as data rates, range, QoS, peak and average power consumption...
The resolution and sampling speed of recently reported SAR ADCs have increased to 11+ ENOB at 50 to 100MS/s [1,2]; however, power efficiency has unfortunately suffered when compared to lower-resolution, lower-speed ADCs. This design targets the same high speed and resolution while simultaneously achieving power efficiency previously associated only with low-speed, low-resolution ADCs. Furthermore,...
The future penetration of long-term-evolution mobile phone services and various data cloud services will continuously accelerate the present traffic evolution. Figure 6.2.1 shows the commercial system capacity evolution of NTT's network over the last 30 years. The transmission capacity of today's Optical Transport Network (OTN) exceeds 1Tbit/s based on the conventional single-core singlemode fiber...
Integrated voltage regulator modules (iVRMs) [1] provide a cost-effective path to realizing per-core dynamic voltage and frequency scaling (DVFS), which can be used to optimize the performance of a power-constrained multi-core processor. This paper presents an iVRM system developed for the POWER8TM microprocessor, which functions as a very fast, accurate low-dropout regulator (LDO), with 90.5% peak...
This paper presents a 4-tap coefficient-error-robust feed-forward equalization (FFE) transmitter (TX) for massively parallel links. Recently, massively parallel links such as on-chip links [1-3], silicon interposers [4,5], or wide I/Os [6] are gaining popularity to meet increasing demand for data transmission with a limited power budget. However, calibration overhead for thousands I/Os to compensate...
Connected personal healthcare, or Telehealth, requires smart, miniature wearable devices that can collect and analyze physiological and environmental parameters during a user's daily routine. To truly support emerging applications (Fig. 18.3.1), a generic platform is needed that can acquire a multitude of sensor modalities and has generic energy-efficient signal processing capabilities. SoC technology...
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