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Vertical integration of layers in a 3D IC exacerbates thermal problem especially for reliability degradation. Low reliability can not only damage the whole circuits but also cause unexpected performance loss. In this paper, we conduct the SA engine with rectangle-STSVs and double-STSVs for improving reliability. The earlier research indicates that the more STSVs a chip has, the better the reliability...
A compact NBTI model is presented by directly solving the reaction-diffusion (RD) equations in a simple way. The new model can handle arbitrary stress conditions without solving time-consuming equations and is hence very suitable for analog/mixed-signal NBTI simulations in SPICE-like environments. The model has been implemented in Cadence ADE with Verilog-A and also takes the stochastic effect of...
Ternary content addressable memory (TCAM), which can store 0, 1 and X in its cells, is widely used to store routing tables in network routers. Meanwhile, NBTI (Negative Bias Temperature Instability) and PBTI (Positive Biased Temperature Instability), which increase Vth and degrade transistor switching speed, have become major reliability challenges. In this paper, we propose a novel TCAM architecture...
In this paper, we investigate a method to achieve cost-effective selective triple modular redundancy (selective TMR) against single event upset (SEU). This method enables us to minimize the vulnerability of the target application circuit implemented on a resource-constrained coarse-grained reconfigurable architecture (CGRA). The key of the proposed method is the evaluation function to determine the...
In sub-65nm CMOS process technologies, networks-on-chip (NoC) are increasingly susceptible to transient faults (i.e., soft errors). To achieve fault tolerance, Triple Modular Redundancy (TMR) and Hamming Error Correction Codes (HECC) are often employed by designers to protect buffers used in NoC components. However, these mechanisms to achieve fault resilience introduce power dissipation overheads...
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