The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
A highly efficient fully integrated passive CMOS rectifier is proposed in this paper. Using four ultra low power and low voltage techniques with proper leakage current compensation technique, this new topology is very high efficient in wide input voltage range of both high voltages and low voltage advanced sub-micron applications simultaneously. In 0.5V AC input signal amplitude the power and voltage...
In this paper we present a novel, extremely simple constant transconductance (gm) technique for a rail-to-rail CMOS amplifier input stage. While the level shifting technique is one of the most popular conventional methods to achieve constant-gm ([1], [6]), in [1], two PMOS source followers, totalling 4 PMOS transistors, are used for level shifting. But in this paper, only one diode connected NMOS...
A self-sufficient Giga-Hertz digitally controlled ring oscillator for clock distribution network is presented in this paper. It features a high supply insensitivity in order to mitigate the additional jitter due to supply noise. This is achieved by inducing a mutual compensation between the oscillation frequency parameters that are affected by the supply voltage variations. The proposed method can...
The paper presents the design of a current-mode control DC-DC buck converter with pulse-width modulation (PWM) mode. The converter achieves a current load ranged from 50 mA to 500 mA over 90% efficiency, and the maximum power efficiency is 95.6%, where the circuit was simulated with the TSMC 0.35 um CMOS process. In order to achieve ultra-wide-load high efficiency, this paper implements with two PMOS...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.