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This paper provides a comprehensive guideline to design high efficient Si thin film solar cells via surface periodic Si nanopillars (SiNP) array texturing. A power conversion efficiency of ~18.1% is predicted to be achievable for the cell consisting of the SiNP array (array periodicity of 500 nm, SiNP diameter of 250 nm, and SiNP length of 1000 nm) on 800 nm thick underlying Si film based on the optical...
The impact of a 60 MeV proton irradiation on the drain induced barrier lowering is investigated for tri-gate FinFETs processed with and without the implementation of different biaxial or uniaxial strain engineering techniques. A contrasting behavior is observed for n- and pFinFETs, which may be associated with the radiation-induced charges in the buried oxide and the influence of the back channel...
This paper presents a low-offset, low-power, high-speed comparator using bulk biasing calibration technique. The adjustment of bulk voltage is realized by analog integration in a feedback loop. The technique can calibrate the offset voltage to small value without reducing speed. The comparator is designed in a standard digital 65nm CMOS technology with 1V supply voltage. The comparator works at 1GHz...
A multiloop method is presented for highly nonlinear ring oscillators in this paper. This circuit permits lower tuning gain through the use of coarse/fine frequency control, which also translates into a lower sensitivity to the voltage at the control lines. A 8-GHz VCO in SMIC 0.18μm 1P6M CMOS technology is designed. The linear tuning range of VCO is from 7.95 to 8.45GHz with the tuning voltage vary...
This paper presents a mobile security SoC to deal with intensive cryptography algorithms for different security protocols. A MIPS-like general processor, a dedicated package processor for fast data package, and multiple security processors for cryptography are integrated in the SoC. Moreover, the performance can be greatly enhanced by the well-designed DTU (Data Transfer Unit), memory architecture...
This paper presents a complementary Lubistor and TFET (CLTFET) inverter, which is composed of a lateral unidirectional bipolar-type insulated-gate transistor (Lubistor) load and a tunneling field effect transistor (TFET) driver. Based on the measurement data of Lubistor and TFET devices published, we have for the first time drawn the load lines and operation point line (Q line) of the new designed...
A novel methodology to statistically analyze the statistics on small device performance is presented for the first time. To verify the accuracy of analysis and modeling, TCAD simulation is used to mimic possible process-induced and random fluctuations. The proposed approach precisely decouples various process dependency of the device electric behavior and predicts the device performance trend induced...
Network-on-Chip (NoC) is the most promising on-chip-interconnection scheme for multi-core processors. In this paper, we propose a novel NoC architecture called Stargon, which is inspired by the Spidergon. A simulation model has been developed to evaluate our architecture. We study the effect of the number of nodes, buffer depth and message length on the performance, and shows that at any situation...
In this paper, we introduce a multiple threads model for video decoding optimization which automatically adjusts the thread priority among decoding threads, and verify the test results on Marvell ARMADA 610 processor. The test results show that the performance of video decoding is improved about 250% comparing with the single thread model, and about 3.5% faster comparing with traditional multiple...
Drift diffusion models have been used extensively by the semiconductor device research community to provide a physics-based approach for the modeling and simulation of electronic devices under various bias conditions. In this article we develop a model based on the drift-diffusion equations for the simulation of Li-air batteries with organic electrolyte. The model is carefully calibrated and takes...
This paper reports modeling the parasitic bipolar device in the 40 nm PD SOI NMOS device considering the floating body effect. Using a unique extraction method, the function of the parasitic bipolar device during transient operations could be modeled. During the turn-on transient by imposing a step voltage from 0 V to 2 V at the gate, the case with a slower rise time shows a faster turn-on in the...
The open-loop de-skewing circuits are traditionally used for fast clock synchronization, but they are unable to deal with the problems induced by run-time variations. This paper presents the design of a skew compensation circuit that can achieve fast lock-in and also perform maintenance operation after lock-in. This circuit is designed on top of the open-loop half-delay-line skew compensation circuit...
A non-trivial nature of the power management circuit design is emphasized based on three case studies. The events of transient latchup and device failure under Charged Device Model (CDM) pulse due to an unexpected current path in power analog circuits are analyzed demonstrating the value of mixed-mode simulation approach.
A methodology is presented for predicting the phase noise of the ΣΔ Fractional-N Frequency Synthesize that is both accurate and efficient based on sampling the noise voltage in the time domain. An accurate Voltage Control Oscillator (VCO) noise model is presented, including both thermal noise and 1/f noise. The behavioral model provides a great speed-up over the transistor level simulation and an...
In this paper a multithreaded processor with hardware context switch mechanism driven by external events is presented for multi-processor system on chip (MPSoC). Combining this mechanism with asynchronous memory access the proposed processor implements Non-preemptive thread scheduling which can assure fairness of threads and optimization for single thread. The overhead of hardware thread switch is...
A structure with an asymmetric interfacial oxide layer is proposed to improve device performance in n-channel MOSFETs. The performance loss from mobility degradation, which results from thin interfacial oxide layers, can be mitigated by using a relatively thick interfacial oxide layer near source regions, while maintaining reasonable short channel effects through a relatively thin interfacial oxide...
In this paper, a novel methodology to fully automate inductor model extraction with guaranteed physical scalability is proposed. A consistent automatic frequency range selection mechanism is added to the direct extraction flow of a 2-π model to ensure the underlying physical trend and scalability. The method is validated with 45 inductor measurements with frequency up to 20 GHz, both good accuracy...
An analog baseband circuitry for a China Mobile Multimedia Broadcasting (CMMB) direct conversion tuner IC is introduced in this paper. It includes an 8th order channel select filter with sharp transition band and utilizes a novel gain-bandwidth-product (GBW) extension technique in designing the low power, high speed operational amplifiers (Op-Amps) of the active-RC filter. A current steering type...
A new extraction method for InGaP/GaAs HBTs based on direct optimization is proposed. Through modification of conventional GP formulation, the variations of transport saturation current and ideal forward transit time versus biases are incorporated into the compact model. Rather than intense and complicated iterative optimization, this new parameter extraction methodology realized the united optimization...
Instruction set development is an effective way to improve processor performance. In SH-4A core enhancement, Prefix instruction is introduced as a technique to enrich function of original instruction. As a result, we have successfully integrated 130 new 32-bit instructions to 16-bit original instruction set and performance of new core is improved up to 43% compared to conventional model.
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