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DMILL technology is being developped for very rad-hard analog-digital applications, such as space and military circuits or as electronics for the future generation of high energy collider (LHC, CERN, Geneva) [3]. Both CMOS and junction (JFET and bipolar) transistors are needed. A new process has been integrated, based on a 1.2 ??m thick silicon film on insulator (SIMOX plus epitaxy), a complete dielectric...
This paper describes a novel electronic device using a two dimensional electron gas produced by the strain-induced electric field in [111] growth-axis Al0.35Ga0.65As/In0.2Ga0.8As/GaAs strained layer structure without the necessity of modulation doping. Two dimensional densities greater than 1011 cm-2 were observed both at room temperaure and 77??K. A field effect tranistor using this strain-layer...
The device structure and the device design methodology to achieve the low voltage-low power sub-0.1 μm MOS devices are discussed. It is shown in the simulation that it is difficult to simultaneously satisfy two requirements to suppress the short channel effect and to improve the device performance in the sub-0.1 μm devices. It is experimentally demonstrated that the short channel effect can be sufficiently...
The main problems which arise in Si CMOS devices while operated at low temperature are investigated. More specifically, the mobility modelling, the influence of impurity freeze-out on LDD resistance, the impact ionization substrate current, the Gate Induced Drain Leakage (GIDL) phenomenon are investigated over a wide range of temperatures (4.2-300 K).
A new type of precision thinned bonded silicon wafer is evaluated for thin film CMOS/SOI applications. SOI wafers with silicon film thickness variations of less than ??2.5 nm are available with choice of substrate doping and buried oxide thickness. CMOS devices fabricated on these wafers have the same carrier mobilities as comparable bulk silicon MOSFETs.
A high frequency, double polysilicon bipolar transistor technology on SIMOX is presented. The SOI substrate consists of a conventional SIMOX wafer upon which a twin epi-layer is grown. A high-frequency bipolar transistor technology is then transferred to this substrate. The initial experimental results are presented and show a high cut-off frequency of some 12.4 GHz. A comparison with identical devices...
This study characterizes the SiO2 etching by two gases C2F6 and CF4, in an experimental high-density reactor. The effect of some experimental parameter variations on the etching rate and F and CF2 radical concentration, has been studied and correlated to the self-induced voltage and the substrate temperature.
The growth of silicon dioxide in pure N2O has been evaluated by using conventional furnace oxidation method. The results have pointed out that neither lightly-doped nor heavily-doped substrates exhibit any self-limited growth behavior. The growth kinetics can be described by the linear-parabolic model. Enhanced oxidation has also been observed on heavily arsenic doped substrates in the pure N2O ambient.
Permeable base transistors (PBT) with metal gates and pn-junction gates have been fabricated with conventional device technology. Measurement results compared with simulations are presented. Although the structures are not optimised, cutoff frequencies of 5.3 GHz for the PBT's with pn-junctions are reached. The PBT's with Schottky gates reach 7 GHz, however, with a lower breakdown voltage. A simple...
We have used a new selective CVD TiSi2 in an advanced CMOS process. Subhalf-micron transistors have been characterised, with results equivalent to devices made with more conventional salicide. Ring oscillators with typical gate a delay times have been fabricated. Finally, fully functional 16K SRAMS and 350 KT ASICs have been fabricated, which indicates the possibility of using this new process for...
With the purpose of determining material parameters of MOS-technology dedicated Shockley-Haynes-structures and MOS varactors, among others, have been integrated on a single chip. By use of a specially developed electronic unit an improved performance of the Shockley-Haynes-Experiment has been achieved. In this paper from the comparison of measurements and analytic simulations the hole mobility ??p...
In this paper NMOS devices characterized by their light emission (Bremsstrahlung) are discussed. A comparison of electrical and optical measurements of NMOS LDD short channel transistors is given. Applications of the optical investigations are the determination of the controllable operating region and the effective channel length of NMOS transistors. As the main point the evaluation of the operating...
Two types of HEMT transistors with 0.2 μm gatelength have been fabricated: pseudomorphic (PM) on GaAs and lattice matched (LM) on InP. An extensive study of the DC and HF-characteristics shows the higher potential of the InP-based devices: extrinsic fT-values up to 141 GHz were obtained. The monolithic integration of the InP LM HEMT's is illustrated by the performance of a coplanar distributed amplifier.
Burst noise (BN) and reverse current are studied in lattice-mismatched InP/ InGaAs/InP photodiodes. BN is related to the presence of an excess current (EC) which sometimes exhibits a clear tunneling behavior. The mean pulse widths, the BN amplitude and the EC are thermally activated. The results suggest that the BN is due to the EC which flows through a crystalline defect and is modulated by an action...
The charge pumping technique is demonstrated and verified to be feasible down to very low temperatures in scaled VLSI MOSFET's. It is shown that the technique can be successfully applied to evaluate the the interface damage due to radiation effects, hot carrier stress and other voltage stress in scaled MOSFET's provided the substrate doping is sufficiently high. A revised model for charge pumping...
A new method of overvoltage protection in the supply path of CMOS circuits is described. The central device of the protection circuit is a CMOS-compatible npn bipolar transistor (BJT) which uses no n+ buried layer and can be manufactured in a simple p-well CMOS process without additional process steps. The device is especially suitable for high-voltage applications in electrically hostile environments...
In order to fabricate metal-insulator-semiconductor (MIS) devices with gate insulating films thinnest than 5 nm, organic monolayers have been grafted on the native oxide layer of silicon wafer. We demonstrate for the first time that a single monolayer of alkyl-trichlorosilane with a thickness in the range 1.9-2.8 nm allows to fabricate a silicon based MIS device with gate leakage current density as...
CMOS latch-up parameters are experimentally studied in the context of deep submicron technology optimization. Holding voltage and triggering current values are measured for both various design rules (N+/P+ distance, structure width) and various process conditions (epitaxial thickness, substrate resistivity, well dose). It is demonstrated that with diffused well, latch-up free behavior can be obtained...
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