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This paper presents an embedded FPGA-based architecture to compute navigation trajectories along a harmonic potential. The goals and obstacles may be changed during computation. Large environments are split into blocks. This approach, together with the use of an increasing precision, enables an optimization of the overall computation time that is theoretically and experimentally studied. Implementation...
In this paper a low level vision processing node for use in existing IEEE 1394 camera setups is presented. The processing node is a small embedded system, that utilizes an FPGA to perform stereo vision preprocessing at rates limited by the bandwidth of IEEE 1394a (400 Mbit). The system is used in a hybrid architecture [5], where it produces undistorted and rectified 512 x 512 images at 2 x 15 frames...
This paper presents the OveRSoC project. The objective is to develop an exploration and validation methodology of embedded real time operating systems for reconfigurable System-On-Chip based platforms. Here, we describe the overall methodology and the corresponding design environment. The method is based on abstract and modular SystemC models that allow to explore, simulate, and validate the distribution...
Curtin University Brailler (CUB) is a Personal Digital Assistant (PDA) for visually impaired people. Its objective is to make information in different formats accessible to people with limited visual ability. This paper presents the design and implementation of two modules: a print-to-Braille translation system and a Braille keyboard controller. The translator implements Blenkhornpsilas algorithm...
Bilinear interpolation is widely used in computer vision for extracting pixel values for positions that lie off the pixel grid in an image. For each sub-pixel, the values of four neighbors are used to compute the interpolated value. This presents a challenge since four pixels must be read from the source image memory for each output pixel. This paper presents an architecture, for implementation within...
Multiprocessor system-on-chip composed of several processing elements will be integrated in embedded systems handling multiple applications with diverse constraints. In order to improve the system performance and temperature profile, dynamic voltage frequency scaling can be applied at processor level. In this article we study an existing approach based on Game Theory, which adjusts at run-time the...
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