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Rapid advances of semiconductor technology lead to higher circuit integration as well as higher operating frequencies. The statistical variations of the parameters during the manufacturing process as well as physical defects in integrated circuits can sometimes degrade circuit performance without altering its logic functionality. These faults are called delay faults. In this paper we consider the...
This paper describes a new self-testing 1-bit full adder. This circuit consists of three polymorphic NAND/NOR gates, two XOR gates and two inverters. The adder is able to detect a reasonable number of stuck-at-faults without the need of any additional logic and diagnostic signals. A fault is indicated by oscillations at the carry-out output. Properties of n-bit carry-propagate adder which is composed...
This paper addresses an efficient concurrent fault detection scheme for the SBox hardware implementation of the AES algorithm. Concurrent fault detection is important not only to protect the encryption/decryption process from random and production faults. It will also protect the system against side-channel attacks, in particular fault-based attacks, i.e. the injection of faults in order to retrieve...
In the work typical ESD failures of integrated circuits and ESD testing methods are presented. Authors describe dependencies between ESD models and different ESD failures. In order to allow more advanced ESD testing of integrated circuits, transmission line pulsing is proposed and its correlation to HBM method described. Finally conclusions based on up-to-date research and test results obtained with...
The paper presents an efficient crosstalk simulator tool "XSIM" and it's methodology for analysis and modeling of signal integrity faults in deep sub-micron chips. The tool is used for analyzing the crosstalk coupling behavior in both defective and defect-free two parallel interconnects. Using the XSIM tool one can also determine the critical values of RLGC parasitics of interconnects and...
With the shrinking technology and increasing statistical defects, multiple design respins are required based on yield learning. Hence, a solution is required to efficiently diagnose the failure types of memory during production in the shortest time frame possible. This paper introduces a novel method of fault classification through image based prognosis of predefined fail signature dictionary. In...
A method for reliable measurement of interconnect delays is presented in the paper. The mode of test vectors generation never induces crosstalks. That is why the delay measurement is reliable. Also, minimization of ground bounce noises and reduction of power consumption during the test is an additional advantage. The presented method allows also localizing and identifying static faults of both stuck-at...
The adoption of systems-on-chip (SoCs) in different types of applications represents an attracting solution. However, the high integration level of SoCs increases the sensitivity to transient faults and consequently introduces some reliability concerns. Several solutions have been proposed to attack this issue, mainly intended to face faults in the processor or in the memory. In this paper, we propose...
Recently, there is a renewed interest in Automatic Test Pattern Generation (ATPG) based on Boolean Satisfiability (SAT). This results from the availability of very powerful SAT solvers that have been developed in the last few years. Studies have shown that SAT-based ATPG tools can clearly outperform classical approaches for hard-to-test faults. While the ATPG problem has to be solved on a circuit,...
In this paper we study complex read faults in SRAMs, a combination of various malfunctions that affect the read operation in nanoscale memories. All the memory elements involved in the read operation are studied, underlining the causes of the realistic faults concerning this operation. The requirements to cover these fault models are given. We show that the different causes of read failure are independent...
A new proposal of a very long instruction word (VLIW) architecture for application specific processors with the built-in-self-repair (BISR) facility realized by means of the variable accuracy arithmetic has been described in this paper. The proposed idea, which is particularly interesting for the portable embedded systems, is based on a novel two accumulator model, which is used in order to obtain...
One of the recently proposed solutions to the problem generation of test pairs' patterns to target delay faults is a multiple input signature register (MISR). The paper proposes a method to minimize control words and to modify the operation diagram of the test pattern generator (TPG) aiming at achieving acceptable test times while ensuring a very high coverage of delay faults. Experimental results...
This paper tries to find out whether commonly used spot defect fault model is still viable for deep sub-micron (DSM) integrated circuits' test and yield model. It is believed that for DSM products spot defects may be no longer major source of yield loss. Results from number of computer experiments are presented and discussed.
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