The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
The functional delay-fault models, which are based on the input stimuli and correspondent responses at the outputs, cover transition faults at the gate level quite well. This statement forms the basis for the analysis and comparison of different methods of design for testability (DFT) using software prototype model of the circuit and to select the most appropriate one before the structural synthesis...
With ever shrinking geometries, growing density and increasing clock rate of chips, delay testing is gaining more and more industry attention to maintain test quality for speed-related failures. The aim of this paper is to explore how functional delay tests constructed at algorithmic level detect transition faults at gate-level. Main attention was paid to investigation of the possibilities to improve...
The test can be developed at the functional level of the circuit. Such an approach allows developing the test at the early stages of the design process in parallel with other activities of this process. The main problem is the quality assessment of the functional test because the implementation of the circuit is not available yet. The paper presents the criteria of the quality assessment of the functional...
Rapid advances of semiconductor technology lead to higher circuit integration as well as higher operating frequencies. The statistical variations of the parameters during the manufacturing process as well as physical defects in integrated circuits can sometimes degrade circuit performance without altering its logic functionality. These faults are called delay faults. In this paper we consider the...
The design complexity of systems on a chip drives the need to reuse legacy or intellectual property cores, whose gate-level implementation details are unavailable. The core test depends on manufacturing technologies and changes permanently during a design lifecycle. The purpose of this paper is to assist the designer in the decision making how to test transition faults of re-synthesized intellectual...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.