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In this work we investigate the performance of fully-depleted silicon-on-insulator (SOI), double-gate (DG) and cylindrical nanowire (CNW) FETs, with the aim of establishing optimization procedures and appropriate scaling rules towards their extreme miniaturization limits. The simulation model fully accounts for quantum electrostatics; current transport is modeled by an improved quantum drift-diffusion...
For the first time, threshold voltage matching was measured on multiple gate transistors, and particularly on n-channel gate-all-around transistors (GAA) with both doped and undoped channel. Good matching performance is demonstrated on doped channel transistors, thanks to the absence of pocket nor halo implants. But most of all, it is shown that suppressing the channel doping allows to suppress the...
We report on the fabrication and measurement of triangular gate-all-around (GAA) and tri-gate devices. On the small triangular cross-section devices we observe a significant enhancement of the extracted carrier mobility (up to ~1000cm2/Vs). We assign this effect to enhanced conduction in the sharp corners of our device, and local volume inversion. The new concept of local volume inversion is supported...
In this paper we propose a novel design for a double gate tunnel field effect transistor (DG TFET), for which the simulations show significant improvements compared with single gate devices with a SiO 2 gate dielectric. For the first time, double gate devices using a high-K gate dielectric are explored, showing on-current as high as 1 mA for a gate voltage of 1.2 V, reduced off-current as low as 0...
In this paper, authors investigated for the first time the effective mobility (mueff) in short-channel FinFET transistors. Dedicated test structures for radio-frequency (RF) split C-V measurements enabled short-channel FinFET C-V measurements, and consequently, accurate effective channel length (Leff) calculation for reliable muff extraction. muff is extracted for FinFETs down to dimensions of 60nm...
The growing importance of nitride-based localised charge-trapping storage has increased the interest in the characterisation of the silicon nitride properties. A new model of the electron motion in the nitride layer is developed, based on Frenkel-Poole detrapping and complete redistribution along the channel. The energy of the traps is evaluated to be around 1.8 eV, with a standard deviation of 0...
A characterization methodology based on a single pulse measurement for evaluating the bias temperature instability (BTI) of high-k devices has been developed. It is shown that the time dependence of the threshold voltage instability extracted from conventional DC and pulse I d-Vg measurements can be affected by the fast charge relaxation process leading to erroneous predictions of lifetime. The proposed...
This work describes a concept of an isolated high-voltage (HV) n-channel LDMOS transistor, which can be used as a high-side switch instead of a HV PMOS transistor. HV n-channel LDMOSFETs for 120V applications (blocking voltage over 150V) were used in the study. The devices were fabricated in a 0.35 mum CMOS-based HV technology. Hot carrier stress experiments (under gate voltage VGS = 10V and drain...
In this paper we present a 3D simulation study of the effect of Fermi level pinning along polysilicon gate grain boundaries on nano-MOSFET variability. Pinning of the Fermi level results in variations between devices depending on the random pattern of grain boundaries within the gate. We present a coherent 3D simulation methodology demonstrating the necessity of statistical simulations. As an illustration...
This paper considers thermoelectric and thermionic converters - also in micro- and nanometer design - for power generation and cooling applications. The potential of thermionic converters is investigated precisely by a new advanced theory with inclusion of backward currents from the 2nd electrode and losses due to thermal radiation and ohmic resistance in the electrodes. The efficiency of thermionic...
Resonant tunneling diodes (RTDs) composed of a heterostructure of fluoride materials on Si substrates were fabricated. In the fabrication process, CaxMg1-xF2 alloy, rather than conventional CaF2, was employed as the initial growth layer on the substrate. The CaxMg1-xF2 initial layer functioned both as a buffer layer for heteroepitaxy and as the barrier layer in a resonant tunneling structure for electrons...
We study layout dependent parasitic capacitance contribution of MOSFETs with 3-dim simulations, and show, that these capacitance contributions are for narrow, short devices comparable to intrinsic contributions. We show that the performance of 65-nm technology is strongly affected by these components, and have therefore been modeled correctly in circuit simulations. We propose a methodology how to...
Single-photon avalanche diodes (SPAD) for 1550 nm wavelength can have InGaAs/InP structure similar to that of avalanche photodiodes of fiber optic systems, but for optimizing the device structure radically different criteria must be adopted. Such criteria are here discussed and a complete experimental characterization of the fabricated device is reported. Remarkable performance is verified also at...
Due to material properties and geometric aspects self heating simulation of silicon devices requires 3D simulation of large structures. Fully coupled electrothermal simulation in three spatial dimensions is extremely memory and CPU time intensive. This work demonstrates a simplification of the approach to a thermal only problem from which much useful information can be extracted. We have applied this...
This paper describes the application of a novel variability-driven statistical analysis methodology to study the stability/performance of SRAM designs in 65nm PD/SOI technology. Our objective is to explore the design-yield space for wordline and bitline voltage assignments in dual supply SRAM while taking into consideration the impact of random process variations. Two possible scenarios are studied:...
We have proposed a novel retinal prosthesis system with three-dimensionally stacked retinal prosthesis chip. The retinal prosthesis chip consists of several LSI chips that are vertically stacked and electrically connected using three-dimensional integration technology. We fabricated retinal prosthesis chip including photodetectors and stimulus current generators. We confirmed that current waveform...
In this paper, we present the characterization and analysis of fixed-pattern noise (FPN) in CMOS image sensor (CIS) pixels fabricated in CMOS 0.18-mum process. The experimental results demonstrate that the dark signal degradation of pinned 4T CIS is mainly due to the dark current generated from the transmission gate (TG) instead of the photodiode (PD). From our investigations of gate voltage/charge...
The physics of carrier transport in a sub-90nm strained SOI n-MOSFET with silicon-carbon (SiC) source/drain (S/D) regions is investigated for the first time. Significant improvement in carrier backscattering coefficient rsat and source injection velocity vinj accounts for the large drive current IDsat enhancement in SiC S/D transistors. The improvement in rsat, is attributed to the modulation of conduction...
This paper reports the effect of shallow-trench-isolation (STI) on generation-recombination (G-R) noise and flicker noise variation in 0.13-μm RF MOSFETs for the first time. The devices with relatively small finger widths (W = 1 μm/Nfinger = 40 and W= 5 μm/Nfinger = 8) presented more pronounced G-R noise compared to those with W= 10 mum/Nfinger = 4 devices. In addition, a wide variation of noise levels...
This paper presents the first demonstration and quantification of the reduced self-heating effects in deep submicron n-MOSFETs on thin strain relaxed buffers (SRB), through the application of the ac conductance technique. Strained Si devices demonstrate a peak enhancement in on-state drain current, Ion ~ 30 %, with this figure falling to 6 % at smaller gate lengths. After applying the ac conductance...
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