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We quantitatively image the doping concentration and the capacitance of a high-voltage lateral metal-oxide-semiconductor transistor device with a channel length of 0.5 μm at 20-GHz frequency using scanning microwave microscopy (SMM). The transistor is embedded in a deep n-well forming a flat pn-junction with the p-substrate, with the shape of the pn-junction resolved in the SMM images. Calibrated...
This work reports the hot-carrier (HC) behavior and specific on-resistance (Ron,sp) optimization of 20∼60 V p-channel LDMOS transistors implemented in a 180 nm HV-CMOS technology. By precise control the implant dose and energy of a p-drift region, which is surrounded by n-type isolation well, one can efficiently optimize the on-resistance and breakdown voltage (BV) trade-off while keeping very low...
In this paper, we discuss the scalable NLDMOS design in a 0.18μm HV-CMOS technology. The design impacts in quasi-saturation are compared between the 25V and 50V NLDMOS to demonstrate the implications in output and fT characteristics. The STI depth sensitivity in DC, ac and HCI characteristics is investigated. The results prove a very robust design, featuring <10% Idlin shift over 10 year lifetime...
This work describes a concept of an isolated high-voltage (HV) n-channel LDMOS transistor, which can be used as a high-side switch instead of a HV PMOS transistor. HV n-channel LDMOSFETs for 120V applications (blocking voltage over 150V) were used in the study. The devices were fabricated in a 0.35 mum CMOS-based HV technology. Hot carrier stress experiments (under gate voltage VGS = 10V and drain...
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