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Nanostructure characterization of carbon nanofibers (CNFs) for on-chip interconnect applications is presented. We propose a novel technique for characterizing interfacial nanostructures of vertically aligned CNFs, optimally suited for cross-sectional imaging with scanning transmission electron microscopy (STEM). Using this technique, vertically aligned CNFs are selectively grown by plasma-enhanced...
This paper reports burn-in test results of Cu/low-K (BD) interconnects on flexible organic substrate (FR-4,0.1mm) and Si substrate. The electrical yields of via chains (via number: 11,182, via size: 0.26 to 0.5 mum) onto flexible organic substrate remain more than 50% and surviving via chains exhibit average resistance shift of 7.3% which is comparable to Si substrate (6.8%) after 524hrs (388hrs/75degC...
Increased packing density and reduced device size leads to increase in the back-end related delays. This happens as a result of increase in the metal resistance due to decreased line-width and increased capacitance due to a higher density of the interconnects. To minimize the impact of interconnect related delays (RC delay) the semiconductor industry had to, as a first order change, look for metal...
Electromigration and stress migration lifetimes are characterized as a function of metal thickness for Cu interconnects fabricated using 0.13 mum process technology. The stress migration lifetime decreases as metal thickness decreases, consistent with previous studies. The electromigration lifetime shows a more complicated dependence on metal thickness. For vias landing on narrow lines, the electromigration...
In this paper, systematic pair bit failure is analyzed in failure bit map of deep-submicron CMOS technology. Tungsten plug corrosion in contacts of stacked contact/metal/via structure is observed from careful analysis of failure bit. Then, some experiments have been carried out to identify and resolve this corrosion failure. This corrosion reaction occurred through the void space, which is formed...
Detection of killer defects is critical to improving yields in VLSI fabrication. Bright and dark-field inspection tools detect both killer and non-killer defects, and in some cases a high level of nuisance defects may adversely affect the ability to monitor and eliminate the real ones that have a detrimental impact on device yield. E-beam inspection tools take advantage of a phenomenon referred to...
Three novel CSP pad designs in a 0.18mum CMOS image sensor Cu interconnect technology were analyzed for use with a wafer level CSP (WLCSP) package. The CSP pad designs used various combinations of available aluminum and tungsten interconnect levels in order to improve the cross-sectional area without increasing the total stack height of the Cu interconnect technology. It was found that by increasing...
During the development and qualification of a 300mm low-k/Cu back end of line (BEOL) technology, the long-term reliability of such interconnects including low-k time-dependent dielectric breakdown (TDDB), Cu electromigration (EM), Cu stress migration (SM), and Cu/low-k thermal behavior are rapidly becoming one of the most critical challenges. In this paper, a comprehensive reliability evaluation for...
The inductance of the on-die interconnection lines may cause voltage resonant effects under electrostatic discharge (ESD) stress. The phase difference of the resonating oscillations along different ESD current flow paths creates a significant local momentary voltage. Information on this inductance enables designers to take into consideration these voltage resonant effects in ESD protection design
We presented a transient electro-thermal analysis with STAP considering self-heating. Thermo-mechanical simulators, e.g. FEDOS, are coupled to provide appropriated input data for electromigration analysis to obtain predictive results. The presented electro-thermal results depict the high temperature gradients close to heat sources and heat sinks. Further regions of high risk of electromigration are...
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