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10nm 2nd generation BEOL technology is described with an optimized illumination system and multi-patterning lithography. While the optimized illumination system offered a possibility to pattern reduced metal pitches in the preferred orientation, difficulties of T-T and T-S patterning still remained. It was overcome by increasing the number of available multi-patterning colors from 2 to 4. First-ever...
For the first time, 20nm DRAM has been developed and fabricated successfully without extreme ultraviolet (EUV) lithography using the honeycomb structure (HCS) and the air-spacer technology. The cell capacitance (Cs) can be increased by 21% at the same cell size using a novel low-cost HCS technology with one argon fluoride immersion (ArF-i) lithography layer. The parasitic bit-line (BL) capacitance...
We discovered that by changing the dielectric capping layer above the phase change memory element we can change the SET speed and data retention of the memory. This allows us, for the first time, to integrate memories of different functions on the same chip with simple processes. By using a low temperature silicon nitride capping material we can get fast SET speed down to 20ns. With a high temperature...
In this paper we demonstrate for the first time the origin of the deep reset and low switching variability obtained on pulse-programmed (100ns) 90nm-size W\Al2O3\TiW\CuCBRAM device operated at 10 μA. To this aim we develop a Quantum-Point-Contact (QPC) model describing the conduction of the CBRAM states down to deep current levels, allowing to estimate the effective size of the defect particles in...
In this paper we demonstrate excellent memory performances of a 90nm CMOS-friendly W\Al2O3\TiW\Cu CBRAM cell integrated in a 1T1R configuration and withstanding the back-end of line thermal budget of 400°C. The cell exhibits low-power and highly controlled set and reset operations, allowing reversible multilevel programming controlled by both the set current and the reset voltage. Low-voltage (<3V)...
In this paper, the characteristic variability in gate-all-around (GAA) silicon nanowire MOSFETs (SNWTs) is experimentally studied. Variation sources in SNWTs are extracted for the first time, taking into account the strongly-confined geometry induced quantum effect, quasi-ballistic effects, as well as the parasitic quantum resistance at the interface of 1D channel and 3D wide S/D regions. The measured...
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