The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
The multi-stack process on wafer-on-wafer (WOW) has been developed. In order to realize the multi-stacked wafer with ultra thinned wafer of less than 10 μm with adhesive polymer, several processes have been optimized. The wafer thickness after back-grinding was controlled within the total thickness variation (TTV) of 1.2 μm on wafer-level of 8 inch. For the side wall of though silicon vias (TSV),...
Pore in low-k SiOCH and vacancies in electroplated Cu buried in damascene structures were studied using monoenergetic positron beams. Doppler broadening spectra of the annihilation radiation and lifetime spectra of positrons were measured for the samples through Cu/low-k damascene processes. The mean pore size in SiOCH decreased after contact etching, but kept constant during Cu metallization. The...
High performance 45-nm Node and its 3D integration employed aggressively thinned down to 7-μm of 300-mm wafer for the Wafer-on-a-Wafer (WOW) application has been succeeded for the first time. The impact of ultra thin wafer on strained transistors and Cu/low-k multilevel interconnects is described. Properties examined include Kelvin and stack chain resistances of Cu interconnects as well as Ion-Ioff,...
Pore characteristics of SiOCH layers in fine-pitch Cu-damascene interconnects were studied using monoenergetic positron beams. Doppler broadening spectra of the annihilation radiation and lifetime spectra of positrons were measured for the samples fabricated with the line/space widths of 0.27/0.27 and 1.08/1.08 mum, respectively. From measurements of the positronium (Ps) lifetimes, the mean pore size...
The fabrication of WOW (wafer-on-a-wafer) with MEMS technology has been developed. A wafer was thinned and stacked on a base wafer. After the TSVs were patterned on the thinned wafer, they were filled by Cu for interconnection. The wafers were bonded with benzocylcobutene (BCB, CYCLOTENETM) as an adhesive material. The BCB layer was also acted as a dielectric layer between top and bottom silicon wafers...
In this study, as one of possible applications of dielectric barrier discharge plasma in atmospheric pressure, annealing a metal thin wire is researched. The discharge plasma can heat the copper wire, and remove extraneous matters. The main purpose is to examine the annealing effect by using atmospheric pressure plasma, and investigate the surface cleaning effect for metal wire. The thin metal wire...
As a practical curing technique of low-k material for 32-nm BEOL technology node, we demonstrated that electron beam (e-beam) irradiation was effective to improve film properties of nano-clustering silica (NCS). We confirmed that by using optimized e-beam cure condition, NCS was successfully hardened without degradation of dielectric constant and the Young's modulus increased by 1.7 times compared...
The chip package interaction (CPI) induced by the mismatch in coefficient of thermal expansion (CTE) between chip and package in a flip chip ball grid array (FCBGA) and its impacts on the mechanical reliability of Cu/ultra low-k interconnect were investigated using finite element analysis (FEA). 3D and 2D multi-level sub-modeling technique was used to link the deformation from the package level to...
Stress induce voiding (SIV) inside and under vias in copper interconnects with ldquowingrdquo-pattern were investigated for 90 nm and 65 nm node processes. The difference of two voidings are the resistance change during acceleration test and the diffusion path. However, common features were found between both types of voiding; the interconnect fails fast as the ldquowingrdquo area grows. Both types...
We tried to evaluate and predict the RC delay variability beyond the 45 nm copper interconnects technologies. The RC delay variability as a normalized delay time distribution, is caused by the line width/height variations due to the manufacturing process fluctuations. In order to evaluate the influence of the resistivity size effect precisely, we improved Fuchs-Sondheimer (F-S) and Mayadas-Shatzkes...
Stress induced voiding inside vias has been investigated in detail using three different kinds of test patterns. Resistance increase which is caused by voiding inside via has been seen larger in "extrusion pattern" than in "wide pattern". The resistance shift depends upon the length of the narrow pattern within the "extrusion pattern". Our new finding is that resistance...
The impact of chip-package interaction (CPI) on the reliability of Cu/low-k interconnects in a flip-chip package for high performance ULSI was investigated using finite element analysis (FEA). A 3D four-level sub-modeling approach was used to analyze the CPI to link the deformation from the package level to the interconnect level. The energy release rate (ERR) and fracture mode at critical interface...
Stress migration (SM) behavior in narrow lines is investigated in detail using different kinds of test patterns. The characteristic of 0.14mum wide line SM failure is different from that of wider line SM failure. The failure rate in the minimum 0.14mum wide line is more than that in 0.2-0.42mum wide lines. The Weibull shape parameter "m" is about 5 in the case of 0.14mum wide line SM failure,...
The impact of chip-package interaction (CPI) on the mechanical reliability of Cu low-k interconnects was investigated using a 3D multi-level sub-modeling method. The analysis was focused on the die attach process for Pb-free solder where a high thermal load will occur during solder reflow before underfilling to maximize the packaging effect. We compared first the CPI for a CVD-OSG (k=3.0) with MSQ...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.