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This paper describes the implementation of an 8-bit Vedic multiplier enhanced in terms of propagation delay when compared with conventional multiplier like array multiplier, Braun multiplier, modified booth multiplier and Wallace tree multiplier. In our design we have utilized 8-bit barrel shifter which requires only one clock cycle for `n' number of shifts. The design is implemented and verified...
In this paper, we quantify the performance analysis of PingPong-128 keystream generator for wireless sensor networks. Although, PingPong-128 is not a standard stream cipher but still PingPong-128 keystream generator is an idea for resource constrained WSNs and can be widely used in the applications of secure communication, where the communication nodes have limited computation processing and storage...
An SST transmitter is described with ground regulation, P-to-N shunting and partially weighted segments for fine granularity level/equalization. Clocks and datapath dissipate 32mW at 7.4Gb/s with an 800mV eye for a power efficiency of 4.32mW/(Gb/s). Measured total jitter is 209.6mUI or 28.3ps at 10-12 BER. Target protocols include PCIe G1/2, XAUI, FC 1/2/4, CEI6 MR and SATA 1/2.
This paper focuses on the design of a 2.4 Gbps to 4.8 Gbps link developed in TSMC65nmG+ technology, for the high speed and high throughput interface between XDRtrade (Extreme data rate) DRAM and ASIC. Applications such as HDTV and high end graphics require high bandwidth interface between controllers and memory. This XDR I/O (XIO) link which is integrated in the controller, interfaces with the XDRtrade...
Supply-noise significantly affects the jitter performance of ring oscillator-based phase-locked loops (PLLs). While the focus of much of the prior art is on supply-noise in oscillators, this paper illustrates that supply-noise in other building blocks also contribute significantly to PLL output jitter. The current design employs a split-tuned PLL architecture wherein the power supply of the building...
We demonstrate a novel, polarization-insensitive scheme for multiwavelength NRZ-to-RZ conversion at 10 Gb/s rate with significant timing jitter suppression. It utilizes an electroabsorption-modulator based optoelectronic oscillator for high quality clock recovery.
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