The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
A large class of robust electronic systems of the future must be designed to perform correctly despite hardware failures. In contrast, today's mainstream systems typically assume error-free hardware. Classical fault-tolerant computing techniques are too expensive for this purpose. This paper presents an overview of new techniques that can enable a sea change in the design of cost-effective robust...
Robust system design ensures that future systems continue to meet user expectations despite rising levels of underlying disturbances. This paper discusses two essential aspects of robust system design: 1. Effective post-silicon validation, despite staggering complexity of future systems, using a new technique called Instruction Footprint Recording and Analysis (IFRA). 2. Cost-effective design of systems...
Low-power circuit operations, such as dynamic voltage scaling and the sleep mode, pose a unique challenge to aging prediction. Traditional aging models assume constant voltage and averaged activity factor, ignoring the impact of the long sleep period, and thus, result in a significant overestimation of the degradation rate. To accurately predict the aging effect in low-power design, this work first...
Transistor aging results in circuit delay degradation over time,and is a growing concern for future systems. On-line circuit failure prediction, together with on-line self-test, can overcome transistor aging challenges for robust systems with built-in self-healing. Effective circuit failure prediction requires very thorough testing to estimate the amount of aging in various parts of a large design...
Carbon nanotubes (CNTs) are grown using chemical synthesis. As a result, it is extremely difficult to ensure exact positioning and uniform density of CNTs. Density variations in CNT growth can compromise reliability of carbon nanotube field effect transistor (CNFET) circuits, and result in increased delay variations. A parameterized model for CNT density variations is presented based on experimental...
Circuit failure prediction predicts the occurrence of a circuit failure "before" errors actually appear in system data and states. This is in contrast to classical error detection where a failure is detected after errors appear in system data and states. Circuit failure prediction is performed concurrently during system operation or during periodic on-line self-test by analyzing the data...
Circuit failure prediction is used to predict occurrences of circuit failures, during system operation, before errors appear in system data and states. This technique is applicable for overcoming major scaled-CMOS reliability challenges posed by aging mechanisms such as Negative-Bias-Temperature-Instability (NBTI). This is possible because of the gradual nature of degradation associated with such...
This paper uses 90nm transistor-level experimental data, device modeling, and circuit simulations to establish the following results: 1. A transistor with defective gate- oxide, i.e., a gate-oxide early-life failure (ELF) candidate transistor, produces gradually degraded drive currents over time before it completely loses its transistor characteristics; 2. The above phenomenon results in gradual increase...
The idea behind circuit failure prediction is to predict the occurrence of a circuit failure before errors actually appear in system data and states. This concept enables a sea change in robust system design by overcoming major reliability challenges such as circuit aging and early-life failures (infant mortality).
Summary form only given. The aim of this paper is to develop enabling technologies and tools spanning multiple abstraction levels to design globally optimized robust systems without incurring the high cost of traditional redundancy. An architecture-aware circuit design technique corrects radiation-induced soft errors in latches, flip-flops, and combinational logic at extremely low-cost compared to...
Circuit failure prediction predicts the occurrence of a circuit failure before errors actually appear in system data and states. This is in contrast to traditional error detection where a failure is detected after errors appear in system data and states. Circuit failure prediction can be performed in multiple ways -the basic principle is to insert a wide variety of "sensors" at various locations...
Summary form only given. Circuit failure prediction predicts the occurrence of a circuit failure before errors actually appear in system data and states. This is in contrast to classical error detection where a failure is detected after errors appear in system data and states. Circuit failure prediction is performed during system operation by analyzing the data collected by sensors inserted at various...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.