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We present a series of circuits for implementing silicon synapses with biologically plausible temporal dynamics and independent global control over gain and time-constant. These types of circuits are useful for implementing synaptic dynamics in neuromorphic networks of spiking neurons, and adaptive or homeostatic mechanisms for controlling the synaptic weights. We demonstrate very compact circuit...
We report pulsed high-k gate dielectric breakdown in various configurations emulating ESD stress in real input/output circuits. The stress on the receiver is of greater concern than is stress on the driver due to different gate oxide areas under stress. Methods to improve pad voltage tolerance for gate oxide breakdown are proposed.
With the advent of miniaturised sensors for various engineering and medical applications there is an increased demand of low-power, low-voltage analog building blocks like opamps and OTAs. Degradation of certain amplifier characteristics with supply voltage is a major concern for low-voltage design and often poses contradictory requirement. CMRR (common mode rejection ratio), one such feature, is...
Large-scale experimental data from 90 nm test chips consisting of 49,152 transistors, and experiments on 90 nm test chips containing inverter chains are used to establish: 1. A gate-oxide early-life failure (ELF, also called infant mortality) candidate transistor produces gradually degraded drive currents over time; 2. A digital circuit path consisting of a gate-oxide ELF candidate transistor experiences...
This paper uses 90nm transistor-level experimental data, device modeling, and circuit simulations to establish the following results: 1. A transistor with defective gate- oxide, i.e., a gate-oxide early-life failure (ELF) candidate transistor, produces gradually degraded drive currents over time before it completely loses its transistor characteristics; 2. The above phenomenon results in gradual increase...
The idea behind circuit failure prediction is to predict the occurrence of a circuit failure before errors actually appear in system data and states. This concept enables a sea change in robust system design by overcoming major reliability challenges such as circuit aging and early-life failures (infant mortality).
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