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In this paper, we present a bus and memory architectures co-synthesis technique. The co-synthesis problem is formulated as an optimization problem, where scheduling, allocation, and binding of tasks are done simultaneously in order to optimize the bus widths, the number of buses, and the memory sizes. As a main contribution, bus and memory architectures are optimized simultaneously by allocating different...
A major trend in a modern system-on-chip design is a growing system complexity, which results in a sharp increase of communication traffic on the on-chip communication bus architectures. In a real-time embedded system, task arrival rate, inter-task arrival time, and data size to be transferred are not uniform over time. This is due to the partial re-configuration of an embedded system to cope with...
A novel approach for illumination normalization is proposed by exploiting the correlation of discrete cosine transform (DCT) low-frequency coefficients to illumination variations. The input image contrast is stretched using full image histogram equalization. Then the low-frequency DCT coefficients (except first) are re-scaled to lower value to compensate the illumination variations. The first (DC)...
This paper presents the characterization of deep-submicron AlGaN/GaN HEMTs for high performance applications, using ATLAS device simulator. The simulations reported in this work involve optimization of the investigated structure. The high RF performance of the device is attributed to the high quality of material and also to optimized device processing. The results are in good agreement with the experimental...
The convergence of telecom and Internet are yet to be matured enough to effectively solve the major challenges, like quality of service, different kinds of charging, and security. IP multimedia subsystems (IMS) techniques are one of the strong contenders to solve the above problems by proposing overlay network architecture. It is imperative to find out an optimum network design to support rapidly...
In this paper, we address the problem of node placement in a hierarchical heterogeneous wireless sensor network. We consider a two-tiered wireless sensor network where the resource constrained lite nodes (LNs) are used for sensing the environment and high-end sophisticated nodes (SNs) are added to aggregate and forward data. We intend to place minimum number of SNs to handle the traffic generated...
Devices using disparate wireless technologies often cannot communicate directly with each other. However, in many practical scenarios such as disaster management and public safety crises, communication amongst dissimilar wireless networks may become a necessity. We investigate the problem of communication in an ad hoc heterogeneous network comprising of several underlying homogeneous networks. Our...
Due to shrinking process geometries and an increasing number of chip components in very deep sub-micron technologies, interconnects emerged as a main limiting factor for performance, die area, and power consumption. Buffer allocation, interconnect congestion, power dissipation in buffered interconnects pose tremendous difficulties on the design process. It is therefore of paramount importance to address...
The current trend for monitoring different parameters in any facility is towards fully integrated surveillance systems using sensor network. For example, sensor network may be deployed over a military installation to monitor temperature, humidity, pressure and surveillance for various equipment or critical regions. Deploying individual sensors node for each parameter would be costly, especially if...
In this paper, we propose multi-channel time division multiple access (MC/TDMA) scheme which provides proportional service differentiation while achieving high throughput in a multichannel wireless network. Proportional service differentiation is achieved by scheduling traffic over multiple non- overlapping channels using the modified open-shop scheduling problem analogy. This analogy allows us to...
We propose a statistical approach for minimizing on-chip communication bus width and number of buses with reduced communication energy under timing yield constraint. The slack is exploited to maximize sharing of buses and to reduce energy by simultaneously scaling the voltage during the communication synthesis. Because of the diversity of applications to be run on a single SoC, there exists variability...
In this paper we analyze how radio frequency identification (RFID) technology can be used to efficiently and cost effectively achieve and improve the tracing and tracking in a monitored area network. In particular we describe implementational issues associated to tracing or tracking of any mobile platform (person, robot etc) equipped with a RFID transmitter. We present a `t-monitored area network'...
This paper presents an energy efficient on-chip communication synthesis for shared bus based architecture. An assumption for the synthesis is that a system has already been partitioned and mapped onto the appropriate modules of a SoC so that size of data to be transferred at each time by an on-chip module is fixed. The problem of communication synthesis is modeled in NLP (nonlinear programming), which...
In a wireless sensor network, sensors can be randomly distributed in order to collect data from a site. In many cases the location of the wireless sensor nodes is required in order to map the collected data to a particular location. Various schemes have been proposed earlier to estimate the location of sensor nodes in a sensor network. However most of these schemes assume the absence of a malicious...
Localization in sensor networks is a prerequisite for associating the sensed phenomenon to a particular location. Various aspects of sensor network localization have recently been studied. However, amongst the vast number of localization schemes proposed, tradeoff between the energy required for localization and resulting accuracy of localization is not addressed. In a highly resource-constrained...
Silicon (Si) microstructures are fabricated comprising a micro-aperture (10-25 /spl mu/m) in a 1.2 k/spl Aring/ silicon nitride membrane connecting two microfluidic compartments. Dielectrophoretic forces are created on-chip, which guide the passage of single CHO cells through the microaperture. When a cell dielectrophoretically traverses the aperture, there is a decrease in the background ionic current...
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