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For 20nm SoC products, we propose an SRAM macro with low dynamic and leakage power. This is achieved by adopting an interleave word-line and hierarchical bit-line scheme, in which minimum portions of circuits are activated when SRAM is accessed. Measured data confirms that the proposed 128kb SRAM realizes 600 mV operation, 2.1 µW/MHz active power and 82 % leakage power reduction.
Current responses due to the strike of ionized particle onto nMOS transistor of 90 nm and 55 nm generation have been analyzed through 3D device simulations. From the current response, duration of charge collection (tcc) is determined, which correlated strongly with the width of erroneous pulse (SET pulse). Causes of the difference between tcc values of 90 nm and 55 nm generation MOSFETs have been...
Soft error phenomena induced by the Sea-level cosmic neutron have been investigated by using a simulation system that covers from an individual MOSFET device level to an LSI-chip level. This system consists of the several kinds of simulation codes/tools, such as a mixed-mode 3D device simulator, SPICE circuit simulator, and analyzing tools of gate-level net-lists. A comprehensive practical simulation...
We analyzed the relation of ESD robustness of the RC-triggered MOSFET Power Clamp to the Gate voltage and Well voltage. If Gate voltage is suppressed low with Well bias applied, the current concentration is avoided, and IT2 increases so that the ESD robustness target can be achieved. By this technology, HBM>2000V, MM>200V and Automobile Specification Transient Latch-up of over 200V performances...
Extreme high-performance n- and pFETs are achieved as 1300 and 1000 uA/um at Ioff = 100 nA/um and Vdd = 1.0 V, respectively, by applying newly proposed booster technologies. The combination of top-cut dual-stress liners and damascene gate remarkably enhances channel stress especially for shorter gate lengths. High-Ion pFETs with compressive stress liners and embedded SiGe source/drain are performed...
For the 45 nm beyond advanced LSI mass-production, accurate dose and beam angle control for the implantation process is highly required. For the purpose the ion beam size and angle monitor was developed and installed in EXCEEDS 000AH new version medium current ion implanter.. The measured results shows the beam size and angle increased at the beam energy decreased, especially for the Y direction beam...
Practical design of double-gate undoped-channel FinFET has been investigated through 3D device simulations considering gate-induced drain leakage (GIDL). Optimization of FinFET structure was carried out for hp45 low standby power (LSTP) device (Lg = 25nm). GIDL is reduced by using gradual and offset source/drain (S/D) profile while degradation of drive current is minimized. Through the optimization...
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