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We derive an analytical model based on circular tunnel paths along the electric field to describe the behavior of a tunnel FET with a junction angle at the source. The model is compared with simulation results and qualitative agreement is observed. We further demonstrate that a small junction angle prevents TFET performance degradation resulting from a high-k spacer. Finally we optimize the junction...
Data retention loss mechanisms in nitride-based localized trapping memory devices are investigated with various electrical measurements and Medici simulations. First, the effect of program and erase cycles on device behavior is determined in terms of bottom oxide degradation and nitride charge profile evolution. Even if a strong degradation of the interface is observed, there is no important impact...
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