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In advanced SOI technologies, the bottom gate voltage plays an important role in achieving the maximum trigger voltage Vt1 of the cascoded drivers. A comparable MOSFET and BJT current handling is needed to ensure maximum Vt1. The minimum and maximum Vt1 window for cascoded driver is shown to range between a single FET Vt1 and twice single FET Vt1.
Low current and high current ESD characteristics of the Poly-Bounded and High-k Metal Gate-bounded ESD diodes with varying stress components are studied in 32 nm SOI technology. It is observed that embedded SiGe (e-SiGe) stress on the anode degrades the ESD protection performance significantly mainly due to the introduction of defects in the active region. Compressive stress liners, tensile stress...
Grounded-body (GB) core-logic/high-speed (HS) and input/output (I/O) silicon-on-insulator pMOSFETs from 65-nm technology are shown to degrade more than floating-body (FB) devices under negative bias temperature instability (NBTI) stress. However, in both cases, worst case degradation occurs when stressed under equal gate and drain voltages (Vg = Vd), whereby degradation is simultaneously induced by...
S-parameter test structures from a 45 nm SOI CMOS technology show total capacitance per perimeter of poly-bounded ESD diodes ranges from ~0.35-0.42 fF/mum, and silicide-block (SBLK) bounded diodes show ~15-20% capacitance reduction. Floating-body or notched-silicon tied-body Gate-Silicided GGNMOS devices show total capacitance per width of ~0.65 fF/um for thin oxide devices, and ~0.72 fF/mum for thick...
A non-self protection ESD scheme using grounded-gate, gate non-silicided (GG-GNS) drain/source silicide blocked (SBLK) ESD NFET offered in 45 nm SOI CMOS technology is presented based on a comprehensive study using the high current pulse characteristics. The results show that with a minimum SBLK width over drain/source, GG-GNS NFET can handle ~3.4 mA/mum current.
Body contacted (BC) core logic/high speed (HS) and input/output (I/O) SOI PMOSFETs from 65 nm technology are shown to have higher degradation than the counterpart floating body (FB) devices under NBTI stress. It is also observed that concurrent HCI-NBTI (hot-carrier injection-negative bias temperature instability) leads to worst case degradation for the I/O and HS SOI p-channel MOSFETs. I/O PMOS devices...
In this paper, the I/O structure described is based on a state of the art 65nm SOI technology designed for SRAM and logic applications (Leobandung et al, 2005). It is a twin-well partially depleted SOI (PDSOI) CMOS technology with gate oxide thicknesses of 1.05nm (SG) and 2.35nm (DG)
It is crucial to minimize the parasitic capacitance at a high-frequency I/O, found in applications such as high-speed serial links and radio receivers. Here, we study the bias-dependent capacitance of a poly-defined SOI diode-a popular ESD protection device according to C. Putnam et al. (2004), C. Entringer et al. (2005), M. Khazbinisky et al. (2005), S. Mitra et al. (2005), and S. Voidman et al....
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