Search results for: Paul Kirsch

Items from 1 to 18 out of 18 results

article

A Correlation Between Oxygen Vacancies and Reliability Characteristics in a Single Zirconium Oxide Metal-Insulator-Metal Capacitor

Hyuk-Min Kwon, Sung-Kyu Kwon, Kwang-Seok Jeong, Sung-Kwen Oh, more

IEEE Transactions on Electron Devices > 2014 > 61 > 8 > 2619 - 2627

A correlation between reliability characteristics and failure mechanisms for time-dependent dielectric breakdown for a single ZrO₂ metal–insulator–metal capacitor has been studied. Frenkel-Poole emission was the dominant mechanism in the high electric field region. The extracted dynamic constant and trap energy level were 4.013 and 0.963 eV, respectively. The variation of

$\alpha $

as a function...

chapter

Connecting RRAM performance to the properties of the hafnia-based dielectrics

Gennadi Bersuker, Brian Butcher, David Gilmer, Paul Kirsch, more

2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC) > 163 - 165

ESSDERC 2013 - 43rd European Solid State Device Research Conference

The connection between the resistive-RAM (RRAM) operational-mechanism, performance, and utilized-dielectric-properties is described. Specifically, the atomic-level description of bi-polar hafnia-based RRAM, which operations involve the repeatable rupture/recreation of a localized conductive path, reveals that its performance is determined by the outcome of the initial forming process; defining the...

chapter

Sub-10nm 1T-1R cell design using HfO_x based ReRAM cell

Jinwoo Noh, Minseok Jo, Chang Yong Kang, David Gilmer, more

2013 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) > 1 - 2

2013 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)

The operation properties of ReRAM for 1T1R structure are simulated using semi-empirical circuit model. From the simulation result, it has been found that the operation of 1T1R structure is seriously affected by various parasitics and the performance of access transistor. For sensing operation, a read circuit using constant current source provided better stability than constant voltage source usually...

chapter

Comprehensive study for RF interference limited 3D TSV optimization

Sang Kyung Lee, Chang Yong Kang, Paul Kirsch, Sitaram Arkalqud, more

2013 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) > 1 - 2

2013 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)

RF interference in Through-Silicon-Via (TSV) 3D chip stacking technology was studied using device parameters from ITRS roadmap. Several new design parameters were defined and optimized based on the calculation. First, chip-to-chip RF interference using TSVs with µ-bump and solder was studied. It was found that the interference was primarily affected by TSV pitch and frequency through the capacitive...

chapter

Effect of fin height of tapered FinFETs on the sub-22-nm System on Chip (SoC) application using TCAD simulation

Chang-Woo Sohn, Chang Yong Kang, Myung-Dong Ko, Rock-Hyun Baek, more

2013 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) > 1 - 2

2013 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)

Table II summarizes the device- and circuit-level assessment using the FinFETs and the planar FETs. Even though the gate control of FinFETs is better than of the planar FETs, further attention should be paid to design H_fin of the FinFETs. SoC blocks such as SRAMs require both high density and low power, so the minimum L_gate will restrict designing H_fin. On the other hand, the analog/RF applications...

chapter

Effects of layout and process parameters on device/circuit performance and variability for 10nm node FinFET technology

Chang Yong Kang, Changwoo Sohn, Rock-Hyun Baek, Chris Hobbs, more

2013 Symposium on VLSI Technology > T90 - T91

2013 Symposium on VLSI Technology

We studied device and circuit performance and their variability for various design and process parameters using TCAD and an analytical RC model. At the 10nm technology node, σC_para and στ_pd became greater while σR_para and σI_on diminish due to lower ρ_c. L_g, H_fin, P_f2f, and P_p2p were found to be key parameters for mitigating variability. Increasing H_fin provides a path for further performance and area...

chapter

Optimal device architecture and hetero-integration scheme for III–V CMOS

Ze Yuan, Archana Kumar, Chien-Yu Chen, Aneesh Nainani, more

2013 Symposium on VLSI Technology > T54 - T55

2013 Symposium on VLSI Technology

Low density-of-states (DOS) of carriers and higher dielectric constants in III–Vs warrants transistor architecture with better electrostatics than conventional bulk FinFETs [1]. Additionally, the integration of III–V FinFETs on 300mm silicon wafers is a key technological challenge due to the large lattice-mismatch between III–Vs and silicon [2]. This paper presents a statistical variability study...

article

High-Speed E-Mode InAs QW MOSFETs With $\hbox{Al}_{2} \hbox{O}_{3}$ Insulator for Future RF Applications

Dae-Hyun Kim, Tae-Woo Kim, Richard J. W. Hill, Chadwin D. Young, more

IEEE Electron Device Letters > 2013 > 34 > 2 > 196 - 198

We demonstrate $L_{g} = \hbox{100}\ \hbox{nm}$ high-speed enhancement-mode (E-mode) InAs quantum-well MOSFETs with outstanding high-frequency and logic performance. These devices feature a 3-nm $\hbox{Al}_{2}\hbox{O}_{3}$ layer grown by atomic layer deposition. The MOSFETs with $L_{g} = \hbox{100}\ \hbox{nm}$ exhibit $V_{T} = \hbox{0.2}\ \hbox{V}$ (E-mode), $R_{\rm ON} = \hbox{370}\ \Omega\cdot\mu\hbox{m}$ ...

article

Development of a Semiempirical Compact Model for DC/AC Cell Operation of ${\rm HfO}_{\rm{x}}$ -Based ReRAMs

Jinwoo Noh, Minseok Jo, Chang Yong Kang, David Gilmer, more

IEEE Electron Device Letters > 2013 > 34 > 9 > 1133 - 1135

A semiempirical model that can simulate dc and pulse (ac) characteristics of filament-type ${\rm HfO}_{\rm{x}}$ -based resistance change random access memory (ReRAM) devices has been developed. Time-dependent device characteristics, because of the dynamic change in the filament size, were emulated using a modified ion migration model. This model describes the difference between SET and RESET operations...

article

High mobility CMOS transistors on Si/SiGe heterostructure channels

Jungwoo Oh, Kanghoon Jeon, Se-Hoon Lee, Jeff Huang, more

Microelectronic Engineering > 2012 > 97 > Complete > 26-28

We have demonstrated high mobility CMOS transistors on Si/SiGe heterostructure channels selectively grown on a Si (100) substrate. Electron and hole mobility is enhanced simultaneously on a single Si/SiGe heterostructure channel by confining electrons in a strained Si channel and holes in a SiGe channel, respectively. Enhanced carrier transports in strained Si or relaxed SiGe channels are confirmed...

chapter

Comparative study of geometry-dependent capacitances of planar FETs and double-gate FinFETs: Optimization and process variation

Chang-Woo Sohn, Chang Yong Kang, Rock-Hyun Baek, Do-Young Choi, more

Proceedings of Technical Program of 2012 VLSI Technology, System and Application > 1 - 2

2012 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)

We quantitatively compared the parasitic capacitance of the planar FETs and the DG FinFETs. Optimization with a fixed Sfin-to-H_fin ratio significantly reduces C_para/W, which renders DG FinFETs comparable to planar FETs. Process variation on W_fin and H_fin should be controlled, otherwise, the C_para uniformity will be worse for DG FinFETs than it is planar FETs.

chapter

Understanding and improving SILC behavior under TDDB stress in full gate-last high-k/metal gate nMOSFETs

Minseok Jo, Chang Young Kang, Kah-Wee Ang, Jeff Huang, more

Proceedings of Technical Program of 2012 VLSI Technology, System and Application > 1 - 2

2012 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)

Stress-induced leakage current (SILC) behavior in full gate-last (FGL) high-k/metal gate devices was evaluated and compared to gate-first (GF) devices. To improve SILC characteristics, Zr was introduced into the high-k bulk region. Incorporating Zr can reduce SILC in both FGL and GF devices by suppressing trap generation in the high-k bulk region under time-dependent dielectric breakdown (TDDB) stress...

article

Impact of NiPt Thickness Scaling on Contact Resistance From Thin-Body FD SOI to Trigate FETs

Kerem Akarvardar, Martin Rodgers, Vidya Kaushik, Corbet S. Johnson, more

IEEE Electron Device Letters > 2012 > 33 > 5 > 631 - 633

The impact of NiPt thickness scaling on total resistance is investigated using short-channel $(L_{g} = \hbox{40}\ \hbox{nm})$ nm high- k metal-gate complementary SOI MOSFETs with fin widths varying from 500 nm (“planar single-gate thin-body FD SOI FET”) to 25 nm (trigate FET). It is shown that limiting the amount of NiPt available for silicidation becomes increasingly critical as fin width scales due...

chapter

Improved high-k/metal gate lifetime via improved SILC understanding and mitigation

Minseok Jo, Chang Young Kang, Jeff Huang, Gennadi Bersuker, more

2011 International Electron Devices Meeting > 18.3.1 - 18.3.4

2011 IEEE International Electron Devices Meeting (IEDM)

For the first time, we identify key factors impacting SILC through a comprehensive reliability study for high-k/metal gate nMOSFET with several mitigating process changes. SILC is increasingly important because higher SILC can distort time-dependent dielectric breakdown (TDDB) lifetime extraction. We find that high-k bulk layer and interfacial layer both contribute to SILC characteristics. We propose...

article

Comparison of Ohmic contact resistances of n- and p-type Ge source/drain and their impact on transport characteristics of Ge metal oxide semiconductor field effect transistors

Jungwoo Oh, Jeff Huang, Yen-Ting Chen, Injo Ok, more

Thin Solid Films > 2011 > 520 > 1 > 442-444

We report the results of a systematic study to understand low drive current of Ge-nMOSFET (metal–oxide–semiconductor field-effect transistor). The poor electron transport property is primarily attributed to the low dopant activation efficiency and high contact resistance. Results are supported by analyzing source/drain Ohmic metal contacts to n-type Ge using the transmission line method. Ni contacts...

chapter

Memory overview and RRAM materials development at SEMATECH

Paul Kirsch

2010 IEEE Hot Chips 22 Symposium (HCS) > 1 - 21

2010 IEEE Hot Chips 22 Symposium (HCS)

This article consists of a collection of slides from the author's conference presentation on the Sematech family of memory materials and products. Some of the specific topics discussed include: the special features, system specifications, and system design for these products; system architectures; applications for use; platforms supported; processing capabilities; memory capabilities; and targeted...

article

Novel Capacitorless Single-Transistor Charge-Trap DRAM (1T CT DRAM) Utilizing Electrons

M Gunhan Ertosun, Kwan-Yong Lim, Chanro Park, Jungwoo Oh, more

IEEE Electron Device Letters > 2010 > 31 > 5 > 405 - 407

For the first time, we propose and experimentally demonstrate a novel single-transistor(1T) DRAM: Capacitorless Single-Transistor Charge-Trap DRAM (1T CT DRAM). The memory operation is obtained by engineering the body of the transistor with CTs by creating intentional electron-trapping zones. This memory makes use of charge traps and uses the existence or absence of electrons in its body instead of...

article

The progress and challenges of threshold voltage control of high-k/metal-gated devices for advanced technologies (Invited Paper)

Hsing-Huang Tseng, Paul Kirsch, C.S. Park, Gennadi Bersuker, more

Microelectronic Engineering > 2009 > 86 > 7-9 > 1722-1727

This paper discusses recent progress in and challenges of threshold voltage control for advanced high-k/metal-gated (HKMG) devices. It presents the impact on threshold voltage (V _t ) control of incorporating La and Al into HKMG devices. A dipole moment model explaining V _t tuning of HfSiON/metal-gated MOSFETs is proposed. In addition, a dual channel scheme that allows La ₂ ...

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