The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
In this work, a DRAM cell based on gated-thyristor having pillar channel and sidewall gate is proposed and investigated through device simulation study. Stored electrons in the base region make a difference in read current lowering potential barrier. It has a fast writing speed under 10 ns because of its mechanism based on thermal injection and highly scalable structure because of self-connected word...
In this paper, we have simulated how the overshoot current in the Resistive-switching Random Access Memory (RRAM) cell is generated and whether the integrated transistor can effectively suppress the overshoot current that can cause degradation of cell endurance. We propose a CMOS-friendly 1T1R fabrication process and proceed with circuit simulation using the process parameters. The simulation shows...
Resistive switching characteristics are investigated for aluminum (Al) inserted NiO resistive switching random access memory (RRAM) by adapting cross-pointed structure. In order to evaluate high-density RRAM with low switching current, we have shown the relationships between various important analytical parameters and reset current reduction. We examine the optimal NiO oxygen content and Al insertion...
In this paper, we have proposed an extraction method to find accurate oxide trap locations and energy level in recessed channel structure such as SRCAT. Analytical models for poly depletion effect and the surface potential variation in the cylindrical coordinate were derived and applied to DRAM SRCAT.
In this paper, a capacitor-less 1T DRAM cell transistor with non-overlap structure and recessed channel is presented. Because of the non-overlap structure between gate and source/drain, GIDL (Gate Induced Drain Leakage) current is efficiently suppressed at hold condition. This results in more than 1 s retention time at 25°C and 100 ms at 85°C.
In this paper, the effects of aluminum (Al) layer and plasma oxidation on TiO2 based bipolar RRAM cell are investigated. The switching behaviors of the several cases in Ir/TiO2/Ir structure are compared with each other from the viewpoint of the effect of inserted Al layer and plasma oxidation time.
Resistive switching characteristics are investigated for NiO resistive switching random access memory (RRAM) by adapting cross-pointed structure. Uniform transition characteristics from high resistive state (HRS) to low resistive state (LRS) are very important to evaluate high reset/set ratio with low switching current. A cell which shows an irregular switching behavior in the initial transition has...
In this work, the reasons for the abnormal corner effect, its impact on the saddle MOSFET device characteristics, and possible approaches to suppress it are examined through simulation. Effectively suppressing the abnormal corner effects is important for application in sub-50 nm high density high performance DRAM cell transistor.
Higher sensing margin and longer retention time are critical issues for commercializing 1T DRAM. In this paper, we propose a body-raised double-gate structure to improve sensing margin and retention time of 1T DRAM and confirm the improvements through 3D simulation. This structure shows about 20% higher sensing margin than the planar structure. We have achieved longer retention time by using high...
The polysilicon depletion effect is one of the key factors that degrade MOSFETs' performance. In this letter, a polysilicon depletion model for recessed-channel (RC) MOSFETs is presented. The model shows good agreement with numerical device simulation results. We also compare the polysilicon depletion effect of RC MOSFETs to that of planar MOSFETs.
A capacitor-less one-transistor DRAM cell with surrounding gate MOSFET with vertical channel (SGVC) using gate-induced drain leakage (GIDL) current for write operation was demonstrated. Compared with the conventional write operation with impact ionization current, the write operation with GIDL current provides high sensing margin owing to higher potential barrier between body and source. To confirm...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.