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Increasing process variation can significantly degrade the write-ability of an SRAM. In this paper, we propose negative bit- line voltage technique to improve cell write-ability without using any on-chip or off-chip negative voltage source. Capacitive coupling is used to generate a transient negative voltage at the low bit-line during write operation. Simulations in 45 nm PD/SOI technology show a...
A methodology for evaluation and optimization of quantization error when porting a pre-existing planar design to FinFET technology is presented. A 52-bit adder from a general purpose processor is used to illustrate the key findings of this study.
A framework for accurately determining the device currents in trapezoidal FinFET devices is presented. The analytical formulation also computes the equivalent threshold voltage of an ideal rectangular fin with iso-current characteristics. The approach easily lends itself to the sensitivity analysis of device currents to variations in the geometric parameters.
A novel 3D computational self-consistent electro-thermal modeling methodology is developed to more precisely analyze leakage currents in nanoscale FinFET devices. The coupled electro-thermal modeling is applied to compare the device performance of poly-Si gate and metal-gate DG-FinFET. Results show very high leakage current in band-edge metal-gate device and poly-Si gate device. Mid-gap metal-gate...
A non-quasi-static (NQS) model accounting for intrinsic carrier propagation delays in both B/E and B/C junctions is implemented in the ASTAP circuit simulator to evaluate the impact of non-quasi-static effects in saturated bipolar circuits. It is shown that while the extra delay introduced by the NQS effects during the turn-on transition is primarily due to the normal mode B/E NQS time constant, the...
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