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Three bits per cell NAND Flash Memory Technology for 30 nm and beyond has been successfully developed with floating gate technology. Tight natural Vth distribution, wide program/erase window, and good cell reliability such as program disturb, endurance and data retention are obtained. 8 level Vth distributions are successfully demonstrated.
The operation of nanoelectromechanical switches is investigated through simulation. A simple methodology based on a 1-D lumped model taking account of the Casimir effect is first proposed to determine a low-voltage actuation window for conventional cantilevers. Results show good agreement with 3-D simulation and prove to be helpful for systematic design. The conventional cantilever shape is then optimized...
Carrier transport in advanced MOSFETs is reviewed. First, electron and hole mobility in (110) MOSFETs are compared with those in (100) MOSFETs. Stress engineering is discussed in terms of energy split and effective mass due to the stress. The optimization of multi-gate MOSFET structure is then considered. As an example of ballistic MOSFETs, the performance and stress engineering of CNT FETs with doped...
A floating gate NAND flash memory technology for 30 nm and beyond has been successfully developed. Wide program/erase window, tight natural threshold voltage (Vth) distribution, and good cell reliabilities such as program disturb, program/erase endurance and data retention are successfully demonstrated, which are essential to realize super MLC.
It is shown that sub-0.1 mum Si nanocrystal bulk MOSFET with thin SiN tunnel insulator is a very strong random noise source used in high-rate small-size random number generation circuit, which is required for cryptograph application in mobile network security. A fast random number generation rate of 0.12 MHz is demonstrated using Si nanocrystal MOSFET and a simple small circuit. It is suggested that...
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