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In this paper, we present a fast low-power low-energy standard public-key cryptography processor for use in power/energy-limited applications. The proposed prime-field elliptic-curve cryptography hardware uses a modified Montgomery modular inverse algorithm to minimize the total calculation time and is completely flexible in terms of the field and curve parameters. The power consumption is minimized...
In this paper, we propose a subthreshold SRAM cell structure which can be read differentially. The main advantage of the cell is its high read current while the static noise margin and power consumption are reasonable. The cell is suitable for high performance applications where the speed is of prime concern. To assess the efficiency of the proposed cell, we compare its characteristics to three subthreshold...
In this paper, we present a very low power prime-field elliptic-curve cryptography (ECC) processor for use in power-limited applications. The proposed ECC processor is flexible in terms of field and curve parameters and the power consumption is minimized by simplifying the architecture of the processor and also trading off speed for power. To assess the power efficiency of the design, we have implemented...
In this paper, we propose 4T FinFET SRAM cells which are robust against NBTI effect. The cells, which only use NMOS or PMOS transistors in their structures, are called 4TLLFBNO and 4TDLFBPO, respectively. The simulation results at iso-area design reveal that 4TLLFBNO has the highest read current and 4TDLFBPO has the least power consumption among different cells. Both cells are expected to be robust...
In this paper, we present a dynamic power management technique for optimizing the use of virtual channels in network on chips. The technique which is called dynamic virtual channels allocation (DVCA) makes use of the traffic conditions and past buffer utilization to dynamically forecast the number of virtual channels that should be active. In this technique, for low(high) traffic loads, a small (large)...
In this paper, we propose an efficient routing algorithm for large scale cluster-based wireless sensor networks. The technique uses two routing levels. In the first level (intra-cluster), cluster members send data directly to their cluster head. In the second level (inter-cluster), the cluster heads use ant colony optimization (ACO) algorithm, which is a biologically inspired paradigm for optimization...
This paper proposes a technique for dynamic power reduction of pipelined processors. Pipelined processors frequently insert NOP instruction to the pipe for generating delay or resolving dependency. Our study shows that the percentage of power consumed by NOP instructions in a pipelined processor is significant. This article studies the detail behavior of NOP instruction and proposes a technique for...
In this paper, a new wide tuning-range LC-VCO circuit working below 2 GHz is presented. The approach is to present a step-by-step design following the established principles in the literature to obtain the minimum phase noise as well as keeping power in a reasonable level The improvement is achieved by using a novel tail stage for enhancement of VCO start-up as well as a new low energy-consuming structure...
In this paper, we introduce a new topology for network on chips which is named multi-level mesh topology. The multi-level mesh topology is basically similar to the 2D-mesh with this difference that we have several meshes that have some common routers. This architecture reduces the latency and the dynamic power consumption in NoCs and can improve the communication throughput in high traffic applications...
In this paper, a double-edge triggered level converter flip-flop (DE-LCFFF) is proposed. The flip-flop makes use of the conditional discharging technique which effectively suppress the dynamic power consumption during transition time and the self-precharging technique to automatically precharge its dynamic node after enough time. An explicit double-edge pulse generator is used to further decrease...
In this paper, a low power low leakage flip-flop called clock gated static pulsed flip-flop (CGSPFF) is proposed. The dynamic power consumption in CGSPFF is reduced by avoiding unnecessary input pulse transitions with clock gating. Two transistors in the main block of the flip-flop are eliminated to achieve low leakage power as well. Using the new clock pulse generator leads to a higher operational...
A pre-computation based technique to lower the power consumption of sequential multipliers is presented. This technique also speeds up the multiplication by reducing the number of clock ticks required to complete a multiplication. The proposed technique may be applied to different sequential multiplication schemes. The benchmark data is extracted from typical DSP applications to show the efficiency...
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