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A 60 GHz monolithic upconversion mixer using a 0.25 mum SiGe-HBT technology with fT and fmaxap200 GHz is demonstrated in this work. The mixer is based on the Gilbert micromixer principle. It has broadband matched single-ended IF and LO inputs. An active LO balun is implemented on-chip to convert the single-ended LO signal into a differential one for driving the Gilbert cell. A shorted stub is inserted...
A low power consumption CMOS complementary cross-coupled LC-tank voltage-controlled oscillator (VCO) is presented. The low power consumption VCO has been implemented with tsmc 0.18 mum 1P6M CMOS technology. A pseudo-resistance transistor is utilized to reduce the DC bias current under a fixed supply voltage. The circuit consumes 2.58 mA from a 1.6 V power supply which saves up to 27% power compared...
This paper describes the detailed design considerations and verification of a 2.35-Gbps burst-mode clock and data recovery circuit. This CDR circuit utilizes a gated-oscillator clock recovery technique with an additional phase locked frequency acquisition circuit which enables it to lock to incoming random data within one or two bits. The CDR circuit was fabricated in 0.18 mum CMOS technology. The...
Millimeter-wave applications such as giga-bps wireless communication and automobile radars are opening a new market. In particular, recent nanometer CMOS circuits realizing millimeter-wave front ends have a potential in markedly reducing the cost of new applications. In this presentation, we will introduce a new millimeter-wave CMOS architecture for short-range radars and high-speed communications...
The development of a lumped element model for monolithic integrated transitions from coplanar probe pads to microstrip line structures is presented for a frequency range up to 90 GHz. Several passive test structures have been fabricated in a five metal layer SiGe BiCMOS process technology. The values of the lumped elements are determined based on measurements and are tabulated in this work. In order...
In this paper, a new method to improve the phase noise performance of LC oscillators is presented. This improvement is achieved by using a novel switched tail stage to improve the loaded quality factor of the circuit effectively with a novel method to minimize phase noise. The results show about 12 dB reduction in phase noise in comparison with recent good works.
The emergence of digital mobile broadband communication systems for voice, data, multimedia and positioning is coupled to the continuous progress of silicon CMOS-technology. Single chip integration with digital part, high integration density, low power consumption, low cost under mass production aspects and excellent RF performance are the current system design challenges. This paper focuses on design...
A designed LNA can support the dualband; 2.3~2.5 GHz and 5.1~5.9 GHz. Switched inductor and switched capacitor is adopted for frequency selection. In switched inductor and capacitor matching network, the optimizing techniques to minimize the insertion loss are explained and self-matched capacitor is proposed for easy flexible impedance and noise matching in the various frequency bands. As using switched...
A CMOS down-conversion folded mixer for the radio frequency (RF) applications is presented. The proposed mixer composes of frequency doubling circuits, transconductance stages, and folded switching stages. With input 1.9 GHz RF signals of -40 dBm driven by 0.948 GHz local oscillation (LO) signals of 0 dBm, the mixer shows a good performance in both the high linearity and the low power consumption...
This paper presents the implementation and performance measurements of RF front-end to reduce the flicker noise and power consumption in TSMC 0.18 um process for 2.4 GHz ISM band. Folded mixers and differential low noise amplifiers (LNA) constitute the proposed RF front-end. Gilbert-cell mixers using the folded technique have been designed for low flicker noise and low power consumption. The folded...
This paper reports the design and fabrication of a membrane-supported spurline band-stop filter. The filter was fabricated using silicon bulk micromachining technique and a CMOS compatible metal/dielectric deposition RF sputtering technique. A closed-form expression of an equivalent value of dielectric constant is also derived and introduced to account for a multi-layer dielectric stack formed as...
Quadrature sub-harmonic mixing to DC or low-IF can be attractive for signal processing at Ka-band. Frequency translation is performed without the need for a local oscillator at the received signal frequency. A lower frequency reference takes advantage of the higher quality of tuning elements and avoids high frequency, power-hungry dividers in the synthesizer. Moreover DC offset and second-order inter-modulation...
In this presentation we will focus on the two main sources of noise in CMOS devices which are of interest for RF circuit, design: flicker noise and thermal noise.
Recent performance advancement in super-scaled CMOS technologies has opened new avenues for implementing RF/MMICs on cost-effective mainstream silicon substrate. This talk addresses critical issues involved in designing those high-frequency circuits under technology constraints of decreasing supply voltage and device gain, increasing device mismatch and metal & substrate losses. The talk will...
A 3.1-10.6 GHz ultra-wideband (UWB) low-voltage low-noise amplifier (LNA) employing only one-stage cascode topology is presented. The voltage-current feedback is used to enhance the bandwidth. The research is based on the TSMC 0.18 mum CMOS processes. A two-section LC resonance configuration is used to arrive at the input and output matching. Measurement results show the following performances: maximum...
Considering the noise correlation term between collector and base current shot noise, there mainly are four noise parameter models of SiGe HBTs, including the unified noise model (UNI), two SPICE noise models (SPN1, SPN2), the thermodynamic noise model (TDN). A comparison of these models was investigated in this work. A SiGe HBT based on BiCMOS process was fabricated and its S-parameters and Minimum...
This paper presents a low noise amplifier (LNA) with high-Q inductors in a wafer-level chip-scale package (WL-CSP) process. Q-factor of inductors has big impacts on characteristics of LNAs, thus we investigate availability of WL-CSP high-Q inductors. A common-source LNA with inductive degeneration is used for discussion. The 5.2 GHz LNA with WL-CSP inductors provides a noise figure of 1.7 dB which...
A novel Low Noise Amplifier (LNA) topology with a transformer-based input integrated matching is here proposed and its application to 60-GHz. This new architecture achieves both input matching and gain boosting in cascode amplifier without requiring the conventional inductive source degeneration, which is known for gain decreasing at high frequency. The transformer has been designed with the 3-D electromagnetic...
We present a topology to provide tolerate quadrature signals in a MB-OFDM UWB frequency synthesizer. This frequency synthesizer is modified to replace a RC-CR network (RC-CR phase shifter) with a frequency division network (dual-mode divider), eliminating amplitude and phase errors of the RC-CR network. The proposed topology obtains superior suppression of image sideband of -15.5 dB when mismatches...
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