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This paper presents a method to salvage malfunctioned bits in a FinFET SRAM array caused by random threshold voltage (Vt) variation. The Vt of pass gates (PGs) is gradually lowered during the read process from the initial high value until the stored data is detected by the sense amplifier. As a result, the best Vt is automatically chosen for each cell and malfunctioned bits of both those too fast...
PVD-TiN gate FinFET SRAM half-cells with different β-ratios and fin-height controlled transistors have successfully been fabricated using orientation-dependent wet etching and selective recess RIE. It was found that read static noise margin (SNM) increases significantly by controlling β from 1 to 2. With further increasing β, read SNM increases slightly. On the other hand, write margin shows weak...
Variability of the TiN FinFET SRAM cell performance is comprehensively studied. It is found that the static noise margin (SNM) variation of the SRAM cell is due to the Vth variation of FinFETs caused by the work function variation (WFV) of the TiN metal-gate. It is experimentally demonstrated that the Vth-controllable independent-double-gate (IDG) FinFET technology successfully compensates not only...
SRAM cells with Vth-controllable independent double-gate (IDG) FinFETs have been successfully fabricated. The performance of the fabricated SRAM cell with various circuit topologies has been investigated comprehensively. Both a reduction of leakage current and an enhancement of read and write noise margins have been successfully demonstrated by introducing the IDG FinFETs into the SRAM cells.
We propose a flexible-pass-gate (Flex-PG) FinFET SRAM to enhance both the read and write noise margins. The flip-flop in the Flex-PG SRAM cell consists of usual FinFETs while its pass gates consist of Vth-controllable four-terminal (4T) FinFETs with independent double-gates. We experimentally demonstrate that the proposed Flex-PG SRAM increases both the read and write margins by controlling the Vth...
An independent-gate four-terminal FinFET SRAM have been successfully fabricated for drastic leakage current reduction. The new SRAM is consisted of a four-terminal (4T-) FinFET which has a flexible Vth controllability. The 4T-FinFET with a TiN metal gate is fabricated by a newly developed gate separation etching process. By appropriately controlling the Vth of the 4T-FinFET, we have successfully demonstrated...
In this paper, we demonstrate CMOS characteristics on a Si(110) surface using surface flattening processes and radical oxidation. A Si(110) surface is easily roughened by OH- ions in the cleaning solution compared with a Si(100) surface. A flat Si(110) surface is realized by the combination of flattening processes, which include a high-temperature wet oxidation, a radical oxidation, and a five-step...
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