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This paper presents a novel low voltage LDMOS structure with low on-resistance based on 0.13 μm CMOS technology. 8 V/9 V Nch LDMOS have only 0.3 μm gate length when the maximum gate operating voltage is 5 V, while the gate length of 5 V CMOS is 0.6 μm to avoid the short channel effect. The obtained specific on-resistance are 1.8 mΩmm2 (8 V Nch LDMOS) and 5.9 mΩmm2 (8 V Pch LDMOS) respectively. Furthermore...
Recently, minimizing the standby power is considered as a critical issue in high-density, mobile CMOS technology. One of the major sources of the leakage current in off-state of ultra-small MOSFET is gate-induced drain leakage (GIDL) which is mainly composed of inter-band and trap-assisted tunneling. By virtues of reduced intra-junction and punch-through leakage currents, threshold voltage controllability,...
IN this paper, various FinFETs with the different fin-width and gate-length were fabricated and characterised using SEM and cross-sectional STEM imaging. It was found that the standard deviations of the Vth of the pMOS and nMOS FinFETs are almost the same and the main Vth variation source was the work function variation of the TiN metal gate. Also, the on-current variation for TiN FinFETs was predominated...
The nanoscale TiN wet etching and its application for FinFET fabrication have been systematically investigated. It is experimentally found that the TiN side-etching can be controlled to be half of TiN thickness with precise time control. By using the developed nanoscale TiN wet etching technique, sub-30-nm physical gate length FinFETs, 100-nm tall fin CMOS inverters and SRAM half-cells have successfully...
Dual metal gate CMOS FinFETs have been integrated successfully by the Ta/Mo interdiffusion technology. For the first time, low-Vt CMOS FinFETs representing on-current enhancement and high-Vt CMOS FinFETs reducing stand-by power dramatically, namely multi-Vt CMOS FinFETs, are demonstrated by selecting Ta/Mo gates for n or pMOS FinFETs with non-doped fin channels. The dual metal gate FinFET SRAM with...
A Ta/Mo interdiffusion dual metal gate technology was successfully introduced to FinFET fabrication. The advantage of the proposed technology was examined by using the gate-first process without a metal-etch off step. The Ta/Mo gated nMOS FinFET with a reduced threshold voltage and the Mo gated pMOS FinFET exhibited symmetrical v alues of (0.31/0.36 V), which are desirable for the FinFET CMOS circuit...
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