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Package stacking, die stacking, wafer stacking, and device stacking are the four different types of three dimensional (3D) technology. Except for package stacking, the other three stacking techniques require special considerations when designing circuits and systems. In this paper, different stacking techniques will first be reviewed, followed by an introduction to the possible applications for 3D...
Integrated microchannel liquid-cooling technology is envisioned as a viable solution to alleviate an increasing thermal stress imposed by 3D stacked ICs. Thermal modeling for microchannel cooling is challenging due to its complicated thermal-wake effect, a localized temperature wake phenomenon downstream of a heated source in the flow. This paper presents a fast and accurate thermal-wake aware thermal...
Non-ideal pattern transfer from drawn circuit layout to manufactured nanometer transistors can severely affect electrical characteristics such as drive current, leakage current, and threshold voltage. Obtaining accurate electrical models of non-rectangular transistors due to sub-wavelength lithography effects is indispensable for DFM-aware nanometer IC design. In this paper, TCAD device simulations...
A new technique for realizing a CMOS low-voltage fully differential sample-and-hold circuit is presented. A low-voltage technique is proposed for CMOS sample-and-hold circuit that avoids the use of low-threshold voltage process, on-chip clock voltage doubler, bootstrapped switch, or switched-opamp technique. For 2.5 MHz input signal frequency, the proposed sample-and-hold circuit exhibits a THD of...
A new technique for realizing a very-high-speed low-power low-voltage CMOS fully differential track-and-hold circuit with low hold pedestal is presented. To achieve high sampling linearity the circuit utilizes linearized input switch. The fully differential design relaxes the trade-off between sampling speed and the sampling precision. The circuit design of major building blocks is described in detailed...
A new technique for realizing a very-high-speed low-power low-voltage CMOS fully differential track-and-hold circuit with low hold pedestal is presented. To achieve high sampling linearity the circuit utilizes improved bootstrapped input switch. The fully differential design relaxes the trade-off between sampling speed and the sampling precision. The circuit design of major building blocks is described...
A new technique for realizing a very-high-speed low-power low-voltage fully differential CMOS track-and-hold circuit with low hold pedestal is presented. To achieve high sampling linearity the circuit utilizes bootstrapped input switch. The fully differential design relaxes the trade-off between sampling speed and the sampling precision. The circuit design of major building blocks is described in...
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