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This paper presents a new method for switching the capacitors in the DAC capacitor array of a successive approximation register (SAR) ADC. By separating the decoding of the most significant bits and the least significant bits, and using two different capacitor arrays with unequal size to determine their values, respectively, the average switching energy of the capacitor arrays is dramatically reduced...
An RF energy scavenging circuit implementing a power matched Villard voltage doubler followed by a switched capacitor DC-DC converter for scavenging ultra-low RF power levels (20 dBm) is presented. Measurement results for the circuit, fabricated in a 130 nm CMOS process, show that 1 V can be generated across a 5 M load from as little as 25.5 Bm of input RF energy at 2.2 GHz. This represents a 9.5...
This paper proposes a new method for switching the capacitors in the DAC capacitor array of a successive approximation register (SAR) ADC. By separating the decoding of the most significant bits and the least significant bits, and using two different capacitor arrays with unequal size to determine their values, respectively, the average switching energy of the capacitor arrays can be dramatically...
A fully custom designed CMOS transceiver chip for high frequency ultrasound imaging applications is described. The chip consists of nine transceiver channels with a programmable beamformer. On the chip, 8 bit 250 MS/s A/D converters digitize analog signals from the transducers and nine 3 Kbyte/channel SRAM store the digitized data for each of the nine channels. The chip was fabricated in a 0.35 mum...
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