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A quad-band 2.5G SoC integrating all the RF, DSP, ARM, audio and other baseband processing functions into a single 65 nm CMOS die is described. The paper focuses on the radio portion mostly, and addresses the challenges of realizing a complete GSM/EDGE SoC with the RF integrated along with the rest of digital baseband circuitry. Several circuit level as well as architectural techniques are presented...
Device scaling is critical for continuing trend of more functionality in a chip. Traditional planar CMOS scaling is increasingly difficult due to limitations in processing and material properties, device structure and reliability. In this paper we will summarize recent advances in these areas, which will enable technology scaling as per Moore's law.
Unique hybrid approach employing both model-based layout optimization and process improvement was successfully developed for reducing rapid thermal anneal (RTA) driven intra die variations. It has been applied to multiple bulk and SOI designs. The model developed herein enables fast estimation of broad-band reflectance of a random layout in 65 nm, 45 nm, and 32 nm nodes and guides reflectance leveling...
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