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A methodology has been proposed recently to predict error rates of cascade structures of blocks in Probabilistic CMOS (PCMOS). It requires characterization of unique probabilistic blocks to predict the error rates of a multi-block cascade structure. While the technique was shown to work for a probabilistic carry-select adder, the technique needs a new model to work in a Wallace Tree Multiplier (WTM)...
Aggressive scaling of CMOS technology has enabled faster and smaller designs but has posed new challenges. In the deep-submicron era, leakage power has become a major contributor to the overall power dissipation of an IC. In this paper, we present a weighted partial Max-SAT (WPMax-SAT) based approach to find the minimum leakage vector (MLV) of a combinational design. In its exact form, this technique...
In this paper we present a new model for characterization of probabilistic gates. While still not mainstream, probabilistic CMOS has the potential to dramatically reduce energy consumption by trading off with error rates on individual bits, e.g., least significant bits of an adder. Our contribution helps account for the filtering effect seen in noise based PCMOS in a novel way. The characterization...
The schematic generator has become a very powerful debug tool in EDA in all of the flows whether it is RTL, Synthesis, formal verification or at the layout level. The paper talks about various challenges in showing a "good" schematic for a spice netlist and then proposes novel algorithms used to generate the schematic. The paper also links various schematic generation stages with techniques...
A five-port two-lane pipelined packet-switched router core with phase-tolerant mesochronous links forms the key communication fabric for an 80-tile network-on-chip (NoC) architecture. The 15FO4 design combines 102 GB/s of raw bandwidth with low fall-through latency of 980 ps. A shared crossbar architecture with a double-pumped crossbar switch enables a compact 0.34 mm2 router layout. In a 65nm eight-metal...
A 275mm2 network-on-chip architecture contains 80 tiles arranged as a 10 times 8 2D array of floating-point cores and packet-switched routers, operating at 4GHz. The 15-F04 design employs mesochronous clocking, fine-grained clock gating, dynamic sleep transistors, and body-bias techniques. The 65nm 100M transistor die is designed to achieve a peak performance of 1.0TFLOPS at 1V while dissipating 98W.
A multicore processor in 65-Nm technology with 80 single-precision, floatingpoint cores delivers performance in excess of a Teraflops while consuming less than 100 W. A 2D on-die mesh interconnection network operating at 5 GHz provides the high-performance communication fabric to connect the cores. The network delivers a bisection bandwidth of 2.56 Terabits per second and a per hop fall-through latency...
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