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This paper presents a novel low voltage LDMOS structure with low on-resistance based on 0.13 μm CMOS technology. 8 V/9 V Nch LDMOS have only 0.3 μm gate length when the maximum gate operating voltage is 5 V, while the gate length of 5 V CMOS is 0.6 μm to avoid the short channel effect. The obtained specific on-resistance are 1.8 mΩmm2 (8 V Nch LDMOS) and 5.9 mΩmm2 (8 V Pch LDMOS) respectively. Furthermore...
A single-chip 11.15times11.15mm2 application and dual-mode WCDMA/HSDPA and GSM/EDGE baseband processor achieves 390MHz in triple-V, low-power 90nm 8M CMOS. A CPU core standby mode with resume cache reduces leakage current of each CPU to 0.04mA when idle. A dynamic bus clock-stop scheme further reduces power consumption. Interconnect buffers allow the chip to support 30f/s VGA video.
In this paper, we demonstrate CMOS characteristics on a Si(110) surface using surface flattening processes and radical oxidation. A Si(110) surface is easily roughened by OH- ions in the cleaning solution compared with a Si(100) surface. A flat Si(110) surface is realized by the combination of flattening processes, which include a high-temperature wet oxidation, a radical oxidation, and a five-step...
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