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In this paper, we present the characterization results of an optimized 4.6 GHz frequency synthesizer ASIC targeted for miniature atomic clock applications. Fabricated into a 130 nm RF CMOS process, the circuit occupies an active area of 2 mm2 and consumes 15 mW of power. The measured phase noise is about −85 dBc/Hz in the range of 2 kHz to 100 kHz frequency offset from the carrier. The circuit was...
The paper presents a new CMOS implementation of the initialization mechanism for Kohonen self-organizing neural networks. A proper selection of initial values of the weights of the neurons exhibits a significant impact on the quality of the learning process. A straightforward realization of the initialization block in software is simple, but in hardware it requires providing the programming signal...
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