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We have fabricated high-performance self-aligned top-gate InGaZnO TFTs with novel silicon-like source and drain (S/D) parasitic resistance (RSD) reduction processes. Ar ion implantation (Ar I/I) formed S/D extension layers and reduced RSD by inducing high-density carriers. First demonstration of self-aligned S/D metallization processes on InGaZnO surface (In-Ti alloy formation), just like silicidation,...
We have successfully suppressed threshold voltage variations due to pattern effect problems and random dopant fluctuation (RDF) using an integrated FSP-FLA technology. The serious problem of the pattern effect in FLA can be solved by using a light-absorber carbon film process, together with FSP-FLA. We estimated the temperature range in our test chip was within 10°C, being the same level obtained...
We have proposed inhibition mechanism of common Al-capping technique for pMOSFET threshold-voltage (Vth) control for the first time, and have established effective Ti-capping technique using metal gate and Hf-based high-k dielectrics. Ti-capping technique can adjust lower Vth than Al-capping one due to the suppression of counter dipole and solid solubility limit in doping. Moreover, Ti-capping technique...
We have developed a carbon absorber process to reduce the pattern effect. This process consists of deposition of carbon, flash lamp annealing (FLA) in an oxygen ambient and SPM-APM wet cleaning. The feature of this process is that the carbon absorber equalizes the light absorption from flash lamps macroscopically and microscopically on the annealed wafer. As a result, we can suppress the pattern effect...
We investigated the influence of extremely high doping concentrations on the sheet resistance of ion implants annealed by FLA. As the implant depth was ultra-shallow and the amount of dopant atoms high, the concentration of dopant near the surface was exceedingly high, above the solid solubility limit, resulting in high Rs. The cause of this is mainly due to the formation of clusters, which was confirmed...
We have presented functional annealing data using the FSP-FLA (flexibly-shaped-pulse flash lamp annealing), together with some examples of the multi-functionality. First, we showed that the FSP-FLA can control thermal budget whilst sustaining high dopant activation, recovering crystalline defects, and controlling thermal diffusion length. Secondly, by combining impulses from conventional FLA and the...
We have developed a device integration scheme for embedded silicon carbon (Si:C) SD structures induced by the solid phase epitaxy (SPE) technique. Our integration scheme comprises a combination of three key processes: carbon ion implantation (I/I) with Ge pre-amorphization implantation (PAI), sRTA and LSA. The guideline of our scheme is as follows. First, carbon I/I with Ge PAI plays large roll in...
We propose the suitable FLA method for pFET device activation by using flexibly-shaped-pulse FLA (FSP-FLA). For the activation annealing by FLA on B without pre-amorphous implantation (PAI) process, increase in preheat temperature before flash is the most effective. By using FSP-FLA, ~1000degC 10-ms preheat was performed. It achieves very shallow and high activated junction without PAI equivalently...
High-performance planar, bulk CMOS technology for 45nm nodes and beyond is reviewed from the point of mobility enhancement techniques and millisecond annealing techniques. Through continuous efforts to increase on-current with the strained techniques while scaling transistor dimensions with millisecond annealing, competitive high-end CMOS technology for 45nm node was realized.
We found that the relatively low temperature millisecond annealing at S/D activation for nFET is enhanced the co-implanted halo activation regardless of sequence of MSA and spike-RTA. Tilt-and-twist extension implantation technique with millisecond extension annealing for pFET was also performed to reduce the parasitic resistance. By combining these technique, an aggressively scaled high-performance...
We applied flash lamp annealing (FLA) in Ni-silicidation to our developed dopant confinement layer (DCL) structure for the first time. DCL technique is a novel stress memorization technique (SMT). We successfully improved the short channel effect (SCE) with keeping a high drive current by FLA in Ni-silicidation. For pMOSFET, 2 layers Ni fully-silicide (Ni-FUSI) was selectively formed on gates, and...
Direct comparison between competitive process flows showed that the eSiGe-S/D-last flow is the most promising CMOS integration process for manufacturing 45-nm technology node and beyond because it has good extensibility with various performance boosters, has fewer process steps and suppresses electrical fluctuations. The eSiGe-S/D-last (after offset spacer + I.I.) flow creates a sufficient process...
Ru underlayer effects on the thermal stability of the magnetic properties in Co-Sm amorphous films have been investigated in terms of its robustness for the thermal-process in the fabrication of GHz band micro-magnetic devices. The anisotropy magnetic field Hk of the Co-Sm film was tending to decrease with an increase in the annealing temperature, but the reduction in Hk due to thermal-process became...
Work on forming high-quality TiN barrier layers by low-pressure chemical vapor deposition (LPCVD) in deep-submicron contacts is reported. A high-quality titanium nitride film was prepared by the photo-assisted LPCVD method using a new organo-titanium compound, Cp2Ti(N3)2, that does not contain chlorine atoms. The film exhibits sufficient barrier effect to withstand 450°C annealing as well...
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