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Contradiction of threshold voltage shift window and endurance severely restricts the application of silicon nanocrystals (Si-NCs). Pre-cycling with higher program/erase (P/E) voltages greatly improves the endurance performance. Baked at 150°C, decreases of stored charges at programmed states have a similar trend, which proves the optimized method does not bring more traps than normal P/E cycling.
Device degradation of solution-based metal-induced laterally crystallized p-type polycrystalline silicon (poly-Si) thin-film transistors (TFTs) is studied under dc bias stresses. While typical negative bias temperature instability (NBTI) or electron injection (EI) is observed under -Vg or -Vd only stress, respectively, no typical hot carrier (HC) degradation can be identified under high -Vd stress...
Device degradation of solution based metal-induced laterally crystallized (MILC) p-type poly-Si thin film transistors (TFTs) is studied under DC bias stresses, which is found to be dominated by negative bias temperature instability (NBTI) mechanism. While standard NBTI or electron injection (EI) is observed under -Vg or -Vd only stress, respectively, a mixed NBTI and EI degradation is observed under...
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