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In this paper, a new structure of silicon tactile imager with SU-8 protective layer is presented. The protective layer is formed on the surface of integrated piezoresistor array to prevent direct contact of the sensor surface to the object. The protective layer is formed individually on each pixel circuit to prevent degradation of the spatial resolution. This tactile imager is fabricated by an established...
We studied the impact of Yttrium and Lanthanum incorporation into HfO2 on reliability (TDDB, PBTI and 1/f noise). They introduce smaller Weibull ?? values and early failure in TDDB, with negative shift in PBTI. They are caused by the negatively charged interstitial oxygen defect generated by Yttrium and Lanthanum incorporation. The effect of Lanthanum is larger than that of Yttrium. It can be explained...
In the through silicon via (TSV) structure for 3-dimentional integration (3DI), large thermal-mechanical stress acts in the BEOL layer caused by the mismatch in thermal expansion coefficient (CTE) of the TSV materials. The resulting high-stress region is thought to be the critical point for the initiation of the cracking or the de-lamination that affects the mechanical reliability. In this study,...
To evaluate tin-whisker growth during thermal cycling tests, a simulation technique for calculating the change in atomic-density distribution of tin caused by a change in temperature, which induces a stress gradient in polycrystalline tin plating, was developed. This technique uses the finite-element method (FEM), molecular-dynamics (MD) simulation, and X-ray diffraction (XRD). Specifically, an FEM...
Stress induce voiding (SIV) inside and under vias in copper interconnects with ldquowingrdquo-pattern were investigated for 90 nm and 65 nm node processes. The difference of two voidings are the resistance change during acceleration test and the diffusion path. However, common features were found between both types of voiding; the interconnect fails fast as the ldquowingrdquo area grows. Both types...
Unlike HBM and MM, CDM robustness is highly dependent on IC layout and packaging. Therefore, IC companies mimic IC IO rings on IO-TEG test chips to select the most appropriate CDM protection concepts (correlation from IO-TEG to final IC??s). This publication highlights pitfalls for this approach. Ensuring consistent substrate and Vss connections drastically improve the correlation.
In this study, we show that increased parasitic capacitance across lateral NPN (LNPN) devices does not necessarily enhance the electro-static discharge (ESD) robustness. Since the drain-bulk displacement current decreases, the LNPN avalanche trigger current increases and the PN junctions fail early. In our case, this happened when the parasitic capacitance between supply lines is around many hundreds...
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