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This paper presents a wide range high efficiency fully integrated switched-capacitor DC-DC converter with fixed output spectrum targeting for noise-sensitive Internet-of-Things (IoT) applications. In order to alleviate the unpredictable output spectrum and the reduced energy efficiency of the conventional pulse-frequency modulation (PFM) and pulse-width modulation (PWM) schemes, fixed output spectrum...
Excess Loop Delay (ELD) induced feedback DAC nonideality is a dominant factor causing error in the transfer function of CT ΣΔ modulators and eventually leading to instability. This paper will present a novel technique which aims to track the amount of excess loop delay, and compensate by using digital logic elements and an RC feedback network. A 2nd order CT ΣΔ modulator with 1-bit DAC was built at...
A novel fixed-Pulse Shape (PS) clock-jitter insensitive Return-to-Zero (RZ) feedback technique in CT ΣΔ modulators is presented. This technique offers a method to reduce the clock-jitter effect in feedback DAC. A switched-RC network and a zero-crossing detector are applied to generate jitter insensitive feedback pulse. This technique was verified in a designed 2nd order CT ΣΔ modulator. A stable 64dB...
A clock generation technique for reducing the clock-jitter sensitivity of Switched current (SI) Return-to-Zero (RZ) DAC in CT ΣΔ modulators is presented in this paper. While realizing the clock-jitter insensitivity, this technique ensures that the feedback period can be utilized more efficiently so that the amplitude of feedback current can be reduced. The proposed technique employs simple digital...
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