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Sub-30 nm TFT CT NAND flash devices have been extensively studied. Although TFT devices were often believed to have much worse performance than bulk devices, our results show that as devices scale down to sub-30 nm, the DC characteristics (such as read current and subthreshold slope (S.S.)) approach those of the bulk devices because sub-30 nm TFT devices often contain no grain boundaries. The memory...
Reliability of charge trapping (CT) devices has been examined in detail, and the path to sub-30nm NAND flash is investigated. All CT devices are vulnerable to edge effects (non-uniform injection and non-uniform Vt along the device width). This degrades both the endurance and the ISPP programming efficiency, but the effect can be minimized by careful engineering. Metal gate and high-K dielectric can...
Floating gate (FG) devices using barrier-engineered (BE) tunneling dielectric have been studied both theoretically and experimentally. Through WKB modeling the tunneling efficiency of various multi-layer tunneling barriers can be well predicted. Experimental results for FG devices with oxide-nitride-oxide (ONO) U-shaped barrier are examined to validate our model. Furthermore, a 1Mb test chip was fabricated...
Hot carrier damage, especially by hot holes, limits the reliability performance of nonvolatile memories (NVMs). The damage creates localized traps in the tunnel oxide and localized interface traps at the oxide/silicon interface. In this paper, we propose a novel method to independently quantify trapped charges localized in the oxide and at the interface. We applied the new method to probe the oxide...
SONOS devices using gate injection programming and erasing have better cycling endurance because the gate oxide is not stressed by P/E operations. This work studies the gate injection behavior in detail using the recently developed gate-sensing and channel-sensing (GSCS) technique. GSCS accurately locates the charge centroid during programming/erasing and reliability tests. For the first time, we...
This paper carefully analyzes various charge-trapping NAND Flash devices including SONOS, MANOS, BE-SONOS, BE-MANOS, and BE-MAONOS. The erase mechanisms using electron de-trapping or hole injection, and the role of the high-k top dielectric (Al2O3) are critically examined. In addition to the intrinsic charge-trapping properties, the STI edge geometry in the NAND array also plays a crucial role in...
Incremental-step-pulse programming (ISPP) is a key enabler for achieving tight VT distribution for MLC NAND Flash. The ISPP characteristics for BE-SONOS NAND Flash are studied extensively in this work. Experimentally we find that the ISPP slope is very close to 1 for BE-SONOS capacitors for a wide range of EOT and O1 variations. A theoretical model is developed to prove that ISPP slope~1 is a universal...
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